Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-10-07
2002-05-21
Nguyen, Chanh (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S098000, C345S100000
Reexamination Certificate
active
06392631
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process for displaying data on a matrix display, more particularly a matrix display consisting of N data lines and M selection lines at the intersections of which are situated image points or pixels. Moreover, the present invention relates to a matrix display of the above type controlled in such a way that the N data lines are grouped into P blocks of N′ data lines each with N=P×N′.
DESCRIPTION OF PRIOR ART
Among matrix displays there are known in particular the liquid crystal screens used in direct vision or projection mode. These screens are generally composed of a first substrate carrying selection lines referenced hereinafter as lines and data lines referenced hereinafter as columns at the intersections of which are situated the image points and of a second substrate comprising a counter-electrode, the liquid crystal being inserted between the two substrates. The image points or pixels consist in particular of pixel electrodes connected by switching circuits such as transistors to the selection lines and to the data lines. The selection lines and the data lines are connected respectively to peripheral control circuits generally termed “drivers”. The line drivers scan the lines one after another and close the switching circuits, that is to say render the transistors of each line passing in succession. On the other hand, the column drivers apply a signal corresponding to an information item to each column, i.e. they charge the electrodes of the selected pixels and modify the optical properties of the liquid crystal contained between these electrodes and the counter-electrode, thus allowing the formation of images on the screen. When the matrix display comprises a limited number of lines and columns, each column is connected by its own connection line to the column drivers of the screen. However, in the case of high-definition screens, the number of columns being very large, use is preferably made of multiplexing between the outputs of the column driver and the columns of the screen so as to reduce the number of tracks. Thus, in French Patent Application No. 96 00259 filed on Jan. 11, 1996, in the name of THOMSON-LCD, there is described a column driver for a matrix display using the principle of multiplexing. This column driver is represented in FIG.
1
. In this case, the columns are grouped into P blocks
1
of N′ columns, namely six columns C
1
, C
2
, C
3
, . . . ,C
6
in the embodiment represented. Each block
1
comprises switching circuits, such as the transistors
3
, one of the electrodes of which is linked to a column Ci and the other electrode of which is connected to the same electrode of the other transistors of the block, this set of electrodes being connected to a data input referenced DB
1
for the first block, DB
2
for the second block, DBP for the last block. The gates of the transistors
3
each receive a demultiplexing signal DW
1
, DW
2
, DW
3
, . . . , DW
6
. Each block has the same structure.
If the liquid crystal display comprises a valve of the SVGA 16/9 2:2 type with 1080 pixels per line for 600 lines, the structure of
FIG. 1
comprises 180 blocks of 6 columns each. Specifically, each sampling signal DW
1
to DW
6
is connected to 180 columns and the video signal consisting of 180 D bits is transferred to the relevant pixel sequentially in blocks of 180 with the aid of 6 control signals DW in the order 1 to 6. Thus, for example, when the signal DW
1
is active, the analogue voltage DB
1
is transferred into pixel
0
associated with column C
1
of the first block, the analogue voltage DB
2
into pixel
6
associated with column C
1
of the second block, the analogue voltage DB
3
into pixel
12
associated with column C
1
of the third block and the analogue voltage DB
180
into pixel
1074
associated with column C
1
of the 180
th
block. Likewise, when the sampling signal DW
2
is active, the analogue voltage DB
1
is transferred into pixel
1
associated with column C
2
of the first block, the analogue voltage, DB
2
into pixel
7
, associated with column C
2
of the second block and so on for the six sampling signals used in the embodiment represented.
When this mode of addressing is used, it is found that, for a grey image, a darker fixed column structure appears which is related directly to the sampling and which is due to line/column coupling. This is because, when the first sampling signal DW
1
activates the 180 gates of the transistors
3
, the content of the video is loaded into pixels
0
,
6
,
12
,
1074
which are then activated. In the same way, the second sampling signal DW
2
will transfer the content of the video into pixels
1
,
7
,
13
,
1075
and so on for the other sampling signals. However, the pixel voltage loaded by the sampling signal DW
2
is not equal to that of the pixels associated with the sampling signal DW
1
on account of the line/column coupling which acts as a capacitive divider. If the sampling signal DW
2
undergoes one coupling, the sampling signal DW
3
will undergo two and so on, as represented in the graph of
FIG. 2
which shows the variation in the pixel voltage as a function of the sampling commands DWi in a block
1
. The pixel voltage therefore decreases with each data transfer.
As represented in
FIG. 3
, a decrease is therefore observed in regard to the luminance for the columns inside a block, with a very large discrepancy in brightness in regard to the pixels corresponding to two adjacent blocks such as pixels
6
and
7
,
13
and
14
, etc. This difference in brightness creates the fixed column structure mentioned above.
SUMMARY OF THE INVENTION
The aim of the invention is therefore to propose a process for displaying data allowing this defect to be remedied.
Accordingly, the subject of the present invention is a process for displaying data on a display consisting of N data lines and M selection lines at the intersections of which are situated image points or pixels, the data lines being grouped into P blocks of N′ data lines each with N=P×N′, each block receiving in parallel one of the P data signals which is demultiplexed on the N′ data lines of said block, characterized in that inside a block, the data lines are addressed according to a spatial order chosen in such a way as to minimize the coupling error between the data lines of two adjacent blocks.
Preferably, the spatial order is chosen in such a way as to obtain a coupling error of
2
&egr; between two consecutively addressed data lines, &egr; representing the coupling error between two adjacent data lines of a block.
According to a preferred embodiment, the spatial order is governed by the function:
R
(
i
)
=
Ent
(
N
′
+
1
)
2
+
(
-
1
)
i
*
Ent
(
i
)
2
where Ent is the integer part of the number with N′ being the number of data lines per block and i varying from 1 to N′.
According to another characteristic of the present invention, the chosen spatial order inside a block is reversed alternately according to the selection lines. Preferably, an addressing, according to the chosen spatial order, is carried out during two successive selection lines and an addressing, according to the reversed spatial order, is carried out during two other subsequent successive selection lines.
The subject of the present invention is also a device for implementing the above process, characterized in that the device essentially includes a programmable logic circuit.
REFERENCES:
patent: 4824212 (1989-04-01), Taniguchi
patent: 4985698 (1991-01-01), Mano et al.
patent: 5426447 (1995-06-01), Lee
patent: 5598178 (1997-01-01), Kawamori
patent: 0319292 (1989-06-01), None
patent: 0434042 (1991-06-01), None
patent: 0836173 (1998-04-01), None
Copy of Search Report.
Bertin Jean-Pierre
Jolly Emmanuel
Alphonse Fritz
Fried Harvey D.
Henig Sammy S.
Nguyen Chanh
Thomson Licensing S.A.
LandOfFree
Process for displaying data on a matrix display does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for displaying data on a matrix display, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for displaying data on a matrix display will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2888571