Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-12-04
2001-11-20
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06321248
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to electronic circuits performing arithmetic operations, and, more particularly, to a process for determining if the format (or size) of the binary result S of an arithmetic operation between two operands A and B, and an input carry digit Cin exceeds the format allowed for this result.
BACKGROUND OF THE INVENTION
Techniques are known in the domain of integrated circuits using calculation units for verifying if the format allowed for the result of an arithmetic operation carried out by an AU (Arithmetic Unit) on two operands A and B and an input carry digit Cin does not exceed a given format. This technique has applications in most calculation units, such as, calculation units included in programmable circuits, such as, a digital signal processor (DSP) or a microcontroller. When it does, an “overflow beyond n bits” occurs and in this case a result saturation may be applied. In general, this type of overflow is determined after the result has been determined, that is, when the AU has finished processing of operands A and B and the input carry digit Cin. In other words, considering
FIG. 1
which schematically shows the various processing steps between when operands A and B and the input carry digit Cin are input into the AU, and when the result S is written in the accumulator, the determination of an overflow is classically done after the calculation step E
2
.
Therefore, to determine if an overflow has occurred, it is necessary to wait until the AU has finished the calculation. In this case there is a time loss that is particularly long if the calculation done by the AU is complex.
SUMMARY OF THE INVENTION
An object of the invention is to overcome this disadvantage. Accordingly, the present invention is directed to a process capable of determining whether or not there will be an overflow of the result format at the same time as the calculation is being done by the AU, and, if so, to propose a saturation value for this result.
More precisely, the invention relates to a process for determining an overflow for an arithmetic operation carried out by an arithmetic unit (AU) on two operands A and B and an input carry digit Cin input to the AU. This process is characterized in that it is executed in parallel to the process done by the AU on the operands A and B and the input carry digit Cin, and before the AU has determined the result of the arithmetic operation.
Throughout the following description, reference will be made to an arithmetic operation carried out by an arithmetic unit (AU). However, this operation may also be done by an arithmetic and logic unit (ALU).
According to one embodiment of the invention, in which the operands A and B are binary numbers, at least one of the operands A and B has m bits and the format of the required result S has n bits (where n<m), the process includes the steps of: considering only the m−n+1 highest order bits denoted A
H
for operand A, and B
H
for operand B and an output carry digit Cout
n−2
of rank n−2; and checking if A
H
, B
H
and Cout
n−2
satisfy a saturation condition, and if so, deducing that the size of the result S exceeds n bits. According to this embodiment, the positive saturation condition in the case of an addition is:
A
H
+B
H
+Cout
n−2
≧1,
and the negative saturation condition in the case of an addition is:
A
H
+B
H
+Cout
n−2
<−1,
where Cout
n−2
is the output carry digit of rank n−2 in the arithmetic operation of A, B and Cin.
According to another embodiment of the invention in which the operands A and B are binary numbers, at least one of the operands A and B has m bits and the format of the searched result S has n bits where n<m, the process includes the steps of:
determining the propagation terms p
i
and generation terms g
i
each defined by a logical relation between components a
i
and b
i
of operands A and B;
considering only the m−n+1 highest order bits, denoted P
H
for propagation terms p
i
and G
H
for generation terms g
i
, and the output carry digit of rank n−2; and
checking if P
H
, G
H
and Cout
n−2
satisfy a saturation condition, and if so deducing that the size of the result S exceeds n bits.
If A is expressed on 40 bits and B on 32 bits with n=32 and m=40, the positive saturation conditions are:
g
31
=1 and (∀i&egr; [39:32], p
i
=1) and Cout
30
=1;
or p
39
=1 and g
39
=0 and (∃i&egr; [38:32], g
i
=1);
or g
39
=0 and (∀i&egr; [39:31], p
i
=0) and Cout
30
=1;
or p
39
=0 and (∃i&egr; [38:31], p
i
=1) and g
39
=0;
and the negative saturation conditions are:
g
39
=1 and (∃i&egr; [38:31], g
i
=0);
or (∀i&egr; [39:31], g
i
=1) and Cout
30
=0;
or p
39
=1 and (∃i&egr; [38:32], p
i
=0) and ∀i&egr; [38:32], g
i
=0
or (∀i&egr; [39:32], p
i
=1) and p
31
=0 and g
31
=0 and
Cout
30
=0
In the following description of the process according to the invention, it will be considered that A and B are two binary numbers, that at least one of A and B has m bits, and that the result S is a binary number with m bits corrected to format with n bits (where A, B and S are coded in two's complement), where n and m depend on the use of the calculation unit. The process according to the invention checks whether the format of the result S that the AU has to calculate will have n bits or less than n bits.
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patent: 5745397 (1998-04-01), Nadehara
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Patent Abstracts of Japan, vol. 15, No. 218, Jun. 4, 1991, and JP 03 062124 A (NEC IC Microcomput Syst Ltd), Mar. 18, 1991.
K. Suzuki et al., “A 2.4-ns, 16-BIT, 0.5-&mgr;m CMOS Arithmetic Logic Unit For Microprogrammable Video Signal Processor LSIs,” Proceedings of the Custom Integrated Circuits Conference, Conf. No. 15, May 9, 1993, pp. 12.04.01-12.04.04.
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Bonnet Claire
Ferroussat Sébastien
Fuin Didier
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Mai Tan V.
STMicroelectronics S.A.
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