Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-02-26
2002-10-15
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S430000, C438S435000
Reexamination Certificate
active
06465325
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to MOSFET semiconductor devices and, more particularly, to a process for depositing and planarizing boron phosphosilicate glass (BPSG) in a narrow trench. The invention can be applied to a power MOSFET containing a trench structure.
BACKGROUND OF THE INVENTION
Borophosphosilicate (BPSG) glass is often used in the manufacture of semiconductor devices, in particular, the manufacture of MOSFETs. It is conventionally employed as an insulator for covering a gate on the surface of the semiconductor device. Typically, a gate is formed over a channel region and separated from the channel by an insulating layer, for example, a gate oxide layer. A BPSG film is conventionally deposited on the gate and heated to cause it to flow, thereby covering the gate and providing a planar insulating surface. Planar surfaces are easier to work with and generate fewer artifacts in further processing. The ability of BPSG to flow and to form a planar surface is a highly desirable feature because it saves a manufacturing step of etching back to planarize an insulating layer. Thus, BPSG is self-planarizing.
Power MOSFET devices and other power devices often rely upon isolation trenches as well as gate trenches. With a gate trench, the gate is buried below the surface and forms in the semiconductor body a channel on the side of the trench between the source on one surface of the die and the drain on the opposite surface. In conventional fabrication, the gates and isolation trenches are formed by etching trenches in silicon, oxidizing the sidewalls, filling the silicon trenches with polysilicon, etching the polysilicon back to a point at or below the surface of the substrate, and then refilling the trenches with a layer of insulating material, typically silicon dioxide or silicon nitride.
Conventional insulator-filled trenches all require a further step of planarization. It would be desirable to replace the silicon dioxide and silicon nitride insulators with BPSG. If a trench were to be filled with BPSG, conceivably the BPSG could be heated to flow and thereby self-planarize as well as fill the trench.
Unfortunately, conventional silane-based BPSG techniques cannot be applied to high aspect ratio silicon trenches, i.e., trenches where the depth:width ratio is greater than 1:1. Etching of polysilicon in a trench produces a surface contour seam shaped like a valley or crater in the center of the polysilicon. Furthermore, conventional BPSG is deposited unevenly around the top corners of a trench, resulting in “breadloafing” that produces voids in the BPSG. When the deposited BPSG material is heated, it fails to flow enough to fill these voids or the seam in the trench. Further processing results in penetration of the voids by impurities that interfere with the performance of the device. Electrical breakdown of the BPSG between the source metal and the polysilicon can result in source-to-gate shorts and leakage. Thus, although BPSG is a desirable insulating material, it cannot be used to fill high aspect ratio trenches by standard procedures.
SUMMARY OF THE INVENTION
The present invention, which provides a method that employs standard deposition and processing equipment to fill trenches with BPSG, is directed to a process for filling a trench having sidewalls and a floor in a semiconductor device or integrated circuit. The process comprises: forming an insulating layer on the sidewalls and floor of a trench in a semiconductor substrate, substantially filling the trench with semiconductor material, removing semiconductor material from an upper portion of the trench, depositing a first layer of BPSG in the upper portion of the trench, heating the substrate to a first temperature greater than about 850° C. and up to about 1100° C., depositing a second layer of silane-based BPSG above the first layer of BPSG, and heating the substrate to a second temperature greater than about 850° C. and up to about 1100° C. In accordance with the invention, the first and second BPSG layers each comprises boron and phosphorus in a weight ratio of boron: phosphorus of greater than 1:1.
REFERENCES:
patent: 5435888 (1995-07-01), Kalnitsky et al.
patent: 5902127 (1999-05-01), Park
patent: 6010948 (2000-01-01), Yu et al.
patent: 6020230 (2000-02-01), Wu
patent: 6214698 (2001-04-01), Liaw et al.
patent: 6265281 (2001-07-01), Reinberg
patent: 2-238647 (1990-09-01), None
patent: 4-129222 (1992-04-01), None
patent: 4-150052 (1992-05-01), None
patent: 7-135247 (1995-05-01), None
patent: 7-254610 (1995-10-01), None
patent: 10-22372 (1998-01-01), None
Benjamin John L.
Linn Jack H.
Ridley Rodney S.
Stensney Frank
Blum David S
Chaudhuri Olik
Fairchild Semiconductor Corporation
Fitzgerald, Esq. Thomas R.
LandOfFree
Process for depositing and planarizing BPSG for dense trench... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for depositing and planarizing BPSG for dense trench..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for depositing and planarizing BPSG for dense trench... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2999367