Process for depositing a layer of material over a substrate

Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Controlling current distribution within bath

Reexamination Certificate

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Details

C204S297010, C204SDIG007, C205S080000, C205S123000, C205S223000

Reexamination Certificate

active

06174425

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to processes and systems for depositing layers on substrates, and more particularly, processes and systems for electroplating metal-containing layers on those substrates
BACKGROUND OF THE INVENTION
Currently semiconductor devices are requiring higher current densities for operation while still resisting electromigration or other reliability problems Copper is being investigated as being a possible alternative to current aluminum or aluminum-copper metalization. One of the most promising methods of depositing copper on a substrate is by using plating methods, such as electroplating
FIG. 1
includes an illustration of a cross-section view of a prior art electroplating system
10
. The system
10
includes a chamber
11
with an outlet port
102
. The system further includes a cup
12
that has an inlet port
112
for receiving a plating fluid and a diffuser
13
within cup
12
. An anode
14
lies between the cup
12
and the diffuser
13
The system
10
further includes a head
15
that has a turntable
151
and clamp fingers
152
. The clamp fingers
152
are the cathode for the system
10
and are typically made of platinized titanium. In the operation of the system
10
, the plating solution
19
enters the cup
12
through the inlet port
112
, flows by the anode
14
, at which point ions from the anode
14
are dissolved into the plating solution
19
. The plating solution
19
continues to flow up through the diffuser
13
to reach the substrate
20
. The plating solution
19
eventually flows over the sides of the cup
12
, down between the walls of the cup
12
and the chamber
11
, and through the outlet port
102
. The anode
14
and clamp fingers
152
are biased to plate the substrate
20
.
During operation of this prior art system
10
, nonuniform deposition typically occurs as illustrated in FIG.
2
. As shown in
FIG. 2
, the semiconductor device substrate
20
has a base material
22
that can be an insulator, a conductor, or a combination of insulators and conductors with a conductive seed layer
24
overlying the base material
22
. Plated material
26
is plated onto the seed layer
24
. Note that the substrate
20
is loading into system
10
upside down. In
FIG. 2
, the substrate has been turned upright so that layer
26
faces the top of FIG.
2
. As shown in
FIG. 2
, the deposition of the plated material
26
is typically thicker near the edge of the substrate
20
and thinner near its center point. This nonuniform deposition causes problems, particularly if the plated material
26
is to be chemically mechanically polished. Polishing typically removes material faster near the center and slower near the edges of the substrate. The combination of the thicker portion of the plated material
26
near the edge of the substrate
20
and the lower polishing rate near the edge accentuates the nonuniformity of the plated material
26
after polishing. During polishing, too much of the underlying base material
22
is removed due to non-ideal polishing selectivity or a ring of residual material is left around the edge of the substrate
20
, where neither are desired.
Electrical robber plates are used in plating printed circuit board substrates. The robber plate is attached to the board and is destructively removed by cutting the piece of the board having the robber plate.
A need exists to create a system that is either more uniform in deposition or is capable of plating slightly more material near the center of the substrate compared to its edges to compensate for the accelerated polishing typically seen near the center of a substrate.


REFERENCES:
patent: 2751340 (1956-06-01), Schaefer et al.
patent: 2859166 (1958-11-01), Grigger
patent: 3880725 (1975-04-01), Van Raalte et al.
patent: 4148707 (1979-04-01), Mayer et al.
patent: 4304641 (1981-12-01), Grandia et al.
patent: 4420382 (1983-12-01), Reidl
patent: 4421627 (1983-12-01), LeBaron
patent: 4466864 (1984-08-01), Bacon et al.
patent: 4678545 (1987-07-01), Galik
patent: 4720329 (1988-01-01), Sirbola
patent: 4879007 (1989-11-01), Wong
patent: 5084153 (1992-01-01), Mosse et al.
patent: 5135636 (1992-08-01), Yee et al.
patent: 5149419 (1992-09-01), Sexton et al.
patent: 5230743 (1993-07-01), Thompson et al.
patent: 5312532 (1994-05-01), Andricacos et al.
patent: 5332487 (1994-07-01), Young, Jr. et al.
patent: 5582708 (1996-12-01), Delfrate et al.
patent: 5620581 (1997-04-01), Ang
patent: 195 47 948 C1 (1996-12-01), None
patent: 500 513 A1 (1992-08-01), None
patent: 0 666 343 A1 (1995-08-01), None
patent: 2 089 838 (1982-06-01), None
patent: WO 87/07654 (1987-12-01), None
Database WPI, Section Ch, Week 7946, Derwent Publications Ltd., London, GB; Class M11, AN 79-83249B, XP002110736 & JP 54 128945 A (Sumitomo Metal Ind Ltd), Oct. 5, 1979 (Oct. 5, 1979) Abstract.
F.A. Lowenheim, Electroplating, McGraw-Hill Book Co., New York, pp 152-155, 160-163, 363-377, 1978 no month available.
R.H. Rousselot, “Current-Distribution Improving Aids”, Metal Finishing, pp 57-63, Mar. 1961.

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