Fishing – trapping – and vermin destroying
Patent
1990-03-26
1991-10-15
Hearn, Brian E.
Fishing, trapping, and vermin destroying
H01L 2172
Patent
active
050574493
ABSTRACT:
A process for creating two thicknesses or gate oxide within a dynamic random memory. The process begins by thermally growing a first layer of gate oxide on a silicon substrate. This first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is then removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. The resultant oxided layer, which comprises multiple-thickness components, is used as a pad oxide layer during a conventional LOCOS operation. Peripheral driver transistors are construction on top of a thin layer of gate oxide so as to optimize their performance, whereas, cell access transistors are constructed on top of a thicker layer of gate oxide so as to minimize row line capacitance. A net increase in row line access speed is thus obtained.
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patent: 4627153 (1986-12-01), Masuoka
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 4675982 (1987-06-01), Noble, Jr. et al.
patent: 4957878 (1990-09-01), Lowrey et al.
S. K. Ghandhi, VLSI Fabrication Priciples, pp. 576-582, 1983.
Gonzalez Fernando
Karniewicz Joseph J.
Lowrey Tyler A.
Chaudhari C.
Fox III Angus C.
Hearn Brian E.
Micro)n Technology, Inc.
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