Process for controlling distance between integrated circuit chip

Details Process for controlling distance between integrated circuit chip Process for controlling distance between integrated circuit chip

1996-01-16

1998-01-27

Graybill, David

Fishing, trapping, and vermin destroying

437208, 437229, 430327, H01L 21027, H01L 2131

Patent

active

057121907

ABSTRACT:
Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.

REFERENCES:
patent: 4704319 (1987-11-01), Belanger et al.
patent: 4706166 (1987-11-01), Go
patent: 4999311 (1991-03-01), Dzarnoski, Jr. et al.
patent: 5126286 (1992-06-01), Chance
patent: 5356838 (1994-10-01), Kim
"Infrared Alignment Fixture For Chip Writer System, " IBM Techincal Disclosure Bulletin, vol. 30, No. 5, 87-90, Oct. 87.

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