Coded data generation or conversion – Converter calibration or testing
Patent
1995-10-26
1997-08-05
Hoff, Marc S.
Coded data generation or conversion
Converter calibration or testing
341172, H03M 110
Patent
active
056547080
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The invention relates to a method for the compensation of component tolerances of a number of similar components, such as capacitors, resistors, current sources and the like, in analog-to-digital converters.
BACKGROUND INFORMATION
The short-channel CMOS processes usually used during the production of analog-to-digital converters are optimized to high transistor component densities and high switching speeds. In particular in the area of ASIC design, however, the further processing of an item of analog input information increasingly requires high-resolution and also precise analog-to-digital converters. As a result of how the process is carried out, high-precision analog components, such as for example resistors and capacitors, are available only in very rare cases. Therefore, in order to achieve accuracies beyond the limit of 8 bits, an adjustment method has to be provided, the type of adjustment essentially determining the quality and reliability of the converter. Binary weighted capacitor arrays are often used in analog-to-digital converters. However, inaccuracies in the weighting ratio of the capacitances inevitably lead to faulty conversion results. These errors result in differential nonlinearities (DNL) which often exceed the specified framework. A 12-bit converter can for example be specified with a precision of 1/2 or 1/4 LSB, it being possible that discrepancies in the capacitive array which controls the upper 8 bits lead to faults of a couple of 10 LSB.
The following printed publications: IEEE CAS-30, pp. 188-190, March 1983 Cancellation Technique for Higher Accuracy A/D Converters", IEEE, Journal of Solid-State-Circuits, Vol. SC-19, No. 2, pp. 266-268, April 1984 1-chip A/D, D/A Converter. All-Digital Linearity Error Correction (LECS)", Electronics and Communications in Japan, Part 2, Vol. 70, pp. 73-84, 1987 Approximation Weighted Capacitor A/D Conversion Technique" ISSCC Dig. Tech. Papers, pp. 38-39, February 1975 Analog-to-Digital Conversion Techniques-Part I", IEEE SC-10 pp. 371-379, December 1979 converters, all of which use an additional digital-to-analog converter. In the case of known correction methods, the capacitor array is corrected in its entirety, but not the individual capacitances independently of the capacitance deviations of the others. Consequently, a recalibration is not possible during normal operation without a relatively long interruption of the conversion process.
European Patent Application No. 0 064 147 A3 describes an analog-to-digital converter in which a multiplicity of similar capacitors are used, where the capacitance values are in each case halved from component to component. The component with the smallest place value is present twice. By applying potentials, a predetermined component is compared with the remaining components of lower place value in that the potential which then appears at the capacitors is compared with a reference potential. In this process, all capacitors are compared with each other successively.
SUMMARY OF THE INVENTION
The compensation method according to the invention has the advantage that as a result of the individual corrections of the individual components, in particular capacitors, independently of the other components, a recalibration of each individual component is possible during normal operation, in each case only very short interruptions of the conversion process being required for this purpose. In addition, the individual compensation of tolerances of the individual components leads, on the whole, to a very precise analog-to-digital conversion over the entire range.
Particularly advantageous is the repetition of the method with interchanged first and second potential, the implementation of a mean-value formation of the two determined correction voltages and the storage of the mean value as the correction value. Possible inaccuracies of the mid-potential are automatically compensated thereby, with the result that the formation of the mid-potential can likewise be carried out relatively inaccurately an
REFERENCES:
patent: 4709225 (1987-11-01), Welland et al.
patent: 4999633 (1991-03-01), Draxelmayr
patent: 5027116 (1991-06-01), Armstrong et al.
patent: 5214430 (1993-05-01), Gulczynski
patent: 5235335 (1993-08-01), Hester et al.
Boehl Eberhard
Gangei Arnd
Tenten Wilfried
Hoff Marc S.
Robert & Bosch GmbH
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