Process for checking the deterministic behavior of a packet...

Details Process for checking the deterministic behavior of a packet... Process for checking the deterministic behavior of a packet...

2008-05-27

2008-05-27

Cardone, Jason D (Department: 2145)

Electrical computers and digital processing systems: multicomput

Computer network managing

Computer network monitoring

C709S234000, C370S229000, C370S252000

Reexamination Certificate

active

07379995

ABSTRACT:
The invention relates to a process for checking the deterministic behavior of a packet switching network comprising subscriber stations connected to each other through at least one switch, this behavior being said to be deterministic in the sense that every packet sent on the network from a source subscriber station joins the destination subscriber station(s) within a limited time, characterized in that the following relation is satisfied for each output port on each switch on the network:∑⁢[1+int⁡((Jitter⁢⁢In)i⁢i+max⁢⁢LatencyBAGi)]*(max⁢⁢⁢frame⁢⁢duration)≤max⁢⁢latencyi=number⁢⁢of⁢⁢virtual⁢⁢links⁢⁢passing⁢⁢through⁢⁢the⁢⁢bufferin which:the max latency value is the maximum residence time in the output buffer of a switch, this value may be different for each switch in the network.BAGi is the minimum time between two consecutive frames belonging to a vertical link i, before they are transmitted on the physical support.(Jitter In) i is the Jitter associated with a virtual link i that represents the time interval between the theoretical instant at which a frame is transmitted, and its effective transmission which may be before or after the theoretical instant.(max frame duration) i is the duration of the longest frame on the virtual link i.

REFERENCES:
patent: 2003/0048754 (2003-03-01), Bruckman
patent: 0579472 (1994-01-01), None
Bennett et al., “Delay Jitter Bounds and Packet Scale Rate Guarantee for Expedited Forwarding”, 2001, IEEE, INFOCOM 2001, pp. 1502-1509.
Chang et al., “Guaranteed Quality-of-Service Wireless Medium Access by Packet-by-Packet Generalized Processor Sharing Algorithm”, 1998, IEEE, pp. 493-497.
Cruz, Rene L., “A Calculus for Network Delay, Part I: Network Elements in Isolation”, Jan. 1991, IEEE Transactions on Information Theory, vol. 37, No. 1, pp. 114-131.
Cruz, Rene L., “A Calculus for Network Delay, Part II: Network Analysis”, Jan. 1991, IEEE Transactions on Information Theory, vol. 37, No. 1, pp. 132-141.
Cruz, R. L., “SCED+: Efficient Management of Quality of Service Guarantees”, 1998, IEEE, pp. 625-634.

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