Process for attaching a silicon chip to a circuit board using a

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step

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438464, 438612, 438667, 438668, 2281805, 434 91, H01L 2128, H01L 2148, H01L 2160, H01K 909

Patent

active

058077669

ABSTRACT:
The present invention features a method and an article of manufacture for directly attaching silicon chips to circuit carriers. Both the method and the article of manufacture feature a dissolvable, thin wafer that is soldered first to the chip and then to the circuit board, completing the connection. The wafer article consists of embedded, spaced-apart, flexible wires that fit the connection footprints of both the chip and the carrier board. The wafer is fashioned from a matrix block having a heat-resistant, dissolvable substance which encapsulates the wires. The matrix is cut into thin slices that are wafer-thin. Each slice or wafer of the matrix carrier is then attached to a chip, using solder with an appropriate melting temperature that is thermally compatible with the chip. The solder attaches one end of the embedded wires to the chip. The other end of the wafer's wires are then matched and soldered to the wire footprint of the circuit board, using another type of solder that melts at a temperature thermally compatible with the circuit board. Afterwards, the dissolvable, encapsulating material is removed from the body of the wafer, leaving the chip attached to the circuit carrier by only, the remaining, interdisposed, flexible wires. In this way a "packageless" package or an "air/copper" package is fabricated.

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patent: 5328087 (1994-07-01), Nelson et al.
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patent: 5509815 (1996-04-01), Jin et al.
"Three-Dimensional Discrete Wire Fan-Out Pattern" IBM Technical Disclosure Bulletin, vol. 27, No. 10A, p. 5572 Mar. 1985.

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