Semiconductor device manufacturing: process – Making regenerative-type switching device – Having field effect structure
Reexamination Certificate
1999-09-02
2001-10-23
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making regenerative-type switching device
Having field effect structure
C438S135000, C438S139000, C438S140000, C438S258000, C257S168000
Reexamination Certificate
active
06306690
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to electronic devices, and more particularly, to a method and apparatus for integrating high and low voltage transistors with a floating gate array.
BACKGROUND OF THE INVENTION
One type of modern nonvolatile memory is the EPROM or EEPROM device that uses floating gate structures. These floating gate memory structures may be integrated into a floating gate array which facilitates interface between the memory cells and control circuitry. The memory cells use channel hot electrons for programming from the drain side and use Fowler-Nordheim tunneling for erasure from the source side. Due to the high voltages frequently used to program and erase the cells, high-voltage peripheral transistors may be implemented to provide an interface between a high-voltage source and the memory cells of the floating gate array. The control logic circuitry of the floating gate array typically functions with a lower operating voltage. Low-voltage peripheral transistors may be implemented to provide the logic circuitry for the array.
To minimize the size of the device, it is desirable to fabricate the peripheral transistors and the floating gate memory cells on a common semiconductor substrate. One approach to manufacturing floating gate arrays with integral peripheral transistors is to form an integrated circuit having a memory cell region, a low-voltage region and a high voltage region. To achieve a desired device scale, the integrated circuit may be formed using shallow trench isolation. Oxide layers to support high and low-voltage transistors are then grown on the substrate surface using the following steps: (1) after deglazing the substrate surface, tunnel oxide, polysilicon and insulator layers are formed on the deglazed substrate surface; (2) the insulator and polysilicon layers are etched from the high and low-voltage regions of the substrate and the tunnel oxide layer is wet deglazed to expose the substrate surface; (3) a high-voltage oxide layer is grown over the high and low-voltage regions of the substrate; (4) the high-voltage oxide layer is wet deglazed from the low-voltage region of the substrate to expose the substrate's surface; and (5) a low-voltage oxide layer is grown in the low-voltage region of the substrate. This process uses three deglazing steps and two oxidation steps.
A problem with this method is that when it is used in conjunction with shallow trench isolation, each deglazing step results in a deeper recession in the oxide within the trenches of the substrate. The deeper this recession becomes, the greater the exposure of the corners of the trenches within the substrate. Requiring three deglazing steps substantially exposes the trench corners, degrading the performance and reliability of the device. For example, exposed trench corners may lead to levels of leakage current which limit the minimum allowable gate length of the device. Leakage current results because the threshold voltage of the device at an exposed corner is lower than the normal threshold voltage of the device. Where the off-voltage of the device is set above the reduced threshold voltage of a trench corner, substantial leakage current results. This phenomenon is commonly referred to as a subthreshold kink in the I/V characteristic of the device. Exposing the trench corners may also degrade the device's gate oxide integrity resulting in a reduction of the gate oxide's charge to breakdown.
Another problem with this method is that it subjects the oxide in the substrate trenches to two oxidations. Each time the substrate is exposed to an oxidizing ambient, oxygen diffuses into the sidewalls of the trench and reacts with the silicon in the sidewalls. As the oxygen and silicon react, oxide is formed which grows away from the trench wall. Because the trenches are already filled with oxide, the existing oxide and the newly-formed oxide compete for the limited space within the trench, causing stress on the oxide within the trench and in the substrate surrounding the silicon trenches. At some point, the stress within the oxide and surrounding silicon causes dislocations in the silicon substrate, which, in turn, increases leakage current. Increasing the number of oxidations, then, ultimately increases the leakage current of the device.
The stress induced in the silicon and the corresponding increase in leakage current becomes more of a problem for silicon that is surrounded by trenches with trench widths less than approximately 3 microns. This is due to the reduced area in the trench, within which additional oxide is growing during the oxidations. The less room there is in the trench for expansion, the higher the stress in the surrounding silicon.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a floating gate memory array integrated with peripheral circuitry is provided that substantially eliminates or reduces the disadvantages associated with prior techniques and processes.
In accordance with one embodiment of the present invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer outwardly from a semiconductor substrate, forming a floating gate layer disposed outwardly from the tunnel oxide layer and forming an insulator layer disposed outwardly from the floating gate layer to create a first intermediate structure. The method further includes the steps of masking a first region and a second region of the first intermediate structure leaving a third region unmasked, removing at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer from the third region and forming a first dielectric layer disposed outwardly from the substrate in a region approximately coextensive with the third region. The second region and the third region are masked, leaving the first region unmasked. Then, at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer is removed from the first region. A second dielectric layer is formed outwardly from the substrate and the first dielectric layer in a region approximately coextensive with the first region and the third regions, respectively.
The present invention has several important technical advantages. The invention involves only two deglazing steps, which decreases the total deglazing time by approximately sixty percent when compared to typical methods of integrating peripheral transistors. Reducing the number of deglazes also reduces trench corner exposure, which decreases leakage current associated with subthreshold kinking and maintains gate oxide integrity. Additionally, the invention reduces the number of oxidations of the low-voltage region to one oxidation. Reducing the number of oxidations minimizes oxide stress within the substrate trenches, substantially eliminating leakage current within the device. Moreover, the invention does not add complexity to the integrated circuit manufacturing process. For example, the additional etch necessary to remove the tunnel oxide, floating gate and insulator layers from the low-voltage region is a non-critical etch. Furthermore, the periphery pattern used to mask the low-voltage region during the additional etch does not require formation of layers beyond what would otherwise be necessary to integrate the periphery transistors.
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Ashburn Stanton P.
Kaya Cetin
Brady III W. James
Fahmy Wael
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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