Process design for wafer edge in VLSI

Details Process design for wafer edge in VLSI Process design for wafer edge in VLSI

1999-08-20

2000-09-05

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

257618, 257635, 257637, H01L 23544, H01L 2906, H01L 2358

Patent

active

061147478

ABSTRACT:
A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the dielectric and conducting films from damage due to wafer handling, storage, or clamping. The dielectric or conducting material is removed from the wafer edge using wafer edge exposure or edge bead rinse methods. The wafer edge exposure method is carried out at the same time the dielectric or conducting layer is being patterned.

REFERENCES:
patent: 4510176 (1985-04-01), Cuthbert et al.
patent: 5168021 (1992-12-01), Arai et al.
patent: 5425846 (1995-06-01), Koze et al.
patent: 5559362 (1996-09-01), Narita

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