Process control computer wherein data and addresses are separate

Details Process control computer wherein data and addresses are separate Process control computer wherein data and addresses are separate

1980-10-27

1983-09-20

Zache, Raulfe B.

Boots, shoes, and leggings

364140, G06F 1546

Patent

active

044059809

ABSTRACT:
A main memory of a process control computer is directly connected to a data input/output unit, and, via a separate address processor, to an address memory. A clock generator is connected to a program memory and the address memory and supplies sequential clock pulses for the execution of the program and for the simultaneous delivery of addresses in each program step. The main memory, which stores the data from the data input/output unit ater the feeding of the addresses from the address processor, supplies the data for the program step to an arithmetic logic unit, which simultaneously receives pulse-frequency driven operation commands from the program memory and feeds the operation results to the data input/output unit and/or to the main memory for storing. A program step counter connected to the program memory continues switching the program steps and controls the output of the operation commands from the program memory. The data bus of the computer is separated from the address bus thereof.

REFERENCES:
patent: 3729716 (1973-04-01), Arulpragasam et al.

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