Etching a substrate: processes – Nongaseous phase etching of substrate – With measuring – testing – or inspecting
Reexamination Certificate
2001-07-23
2004-09-14
Vinh, Lan (Department: 1765)
Etching a substrate: processes
Nongaseous phase etching of substrate
With measuring, testing, or inspecting
C216S059000, C216S079000, C438S706000
Reexamination Certificate
active
06790376
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of using weight or mass measurements to control various semiconductor manufacturing processes, and systems for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g, microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
In the process of forming integrated circuit devices, millions of transistors are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
A variety of processes may be used to form the process layers above the substrate. For example, a process layer may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), thermal growing, etc. Moreover, the process layers may be comprised of a variety of materials, e.g., a metal, polysilicon, silicon dioxide or other various types of insulating material having a dielectric constant less than 5.0, etc. The thickness of the resulting process layer is, typically, very important. If the thickness of the layer falls outside of a relatively tightly controlled acceptable range, then one or more subsequent processes and/or the performance of the completed integrated circuit device may be adversely impacted or compromised.
In an effort to control the deposited thickness of a process layer, most modem semiconductor manufacturing facilities perform a deposition process (or thermal growth process if appropriate) for a fixed duration of time. During this process, it is assumed, based upon empirical evidence of the deposition rate of the given process, that a process layer of a given thickness has been formed. However, these assumed deposition rates vary depending upon a variety of factors, such as the cleanliness of the deposition tool, the quality of the gas supplied to the process, the precise power settings used, etc. Moreover, these variations may extend across one or more deposition tools that are intended to be used to form similar process layers on different substrates. As a result, it is difficult to control the as-formed thickness of the process layer based upon the duration of the deposition process. Direct measurement of the thickness of the process layer after or as it is being formed is also problematic given the nature of the metrology tools involved. For example, in using optical metrology, there may be interfering lights, inspection windows may fog, etc. Moreover, dielectric layers tend to excessively refract light used during such optical metrology.
Additionally, another problem that is encountered in semiconductor manufacturing involves determining when to stop an etching process. Ideally, an etching process should be stopped at the precise point where all of the desired material has been removed, and no damage has occurred to the underlying structure. Current etching processes may be performed for a fixed duration (a timed etch process) or they may be endpointed using a variety of techniques, e.g., an analysis of gases emitted during the process and/or an optical metrology tool that detects when the underlying layer is visible, at least in the section where the optical metrology tool is focused. However, these endpoint techniques may prove inadequate in certain situations. Moreover, as with the deposition processes described above, the etch rate of various processes may vary depending upon the cleanliness of the etch tool, the quality of the gases used, etc.
In some situations a sensor, such as an acoustic wave sensor, has been mounted on the wall of a deposition chamber to determine the extent of material build-up on the wall of the chamber, i.e., the cleanliness of the chamber. For example, see the presentation entitled “Wall Deposition and Cleaning Studies in Polysilicon Plasma Etch Chambers Using a Quartz Crystal Microbalance,” dated May 1995, that is submitted herewith in an appropriate information disclosure form. Using input from the sensor, a decision may then be made as to when cleaning of the chamber is required. Prior to the use of such sensor information, deposition chambers were cleaned on an established schedule, i.e., after a given number of wafers had been processed. However, using such a cleaning protocol resulted in performing time-consuming cleaning operations when it may have been unnecessary. As a result, manufacturing efficiencies may have been reduced.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
In general, the present invention is directed to methods of using weight or mass measurements to control various semiconductor manufacturing processes, and systems for accomplishing same. One illustrative method comprises providing a substrate, performing a deposition process to form a process layer above the substrate, determining a weight or mass of the process layer formed above the substrate, and controlling at least one parameter of the deposition process based upon the determined weight or mass of the process layer.
Another illustrative method comprises providing a substrate having a process layer formed thereabove, performing an etching process to remove at least a portion of the process layer, determining a weight or mass of the removed portion of the process layer, and controlling at least one parameter of the etching process based upon the determined weight or mass of the removed portion of the process layer.
One illustrative system in accordance with the present invention comprises a deposition tool for performing a deposition process to form a process layer above a substrate, a pressure sensor in contact with the substrate for sensing a pressure induced as a result of the process layer formed above the substrate, and a controller for controlling at least one parameter of the deposition process based upon the sensed pressure. In other illustrative embodiments, a scale or balance may be used to measure the weight or mass, respectively, of the material added during the deposition process.
Another illustrative system in accordance with the present invention comprises an etch tool for performing an etching process to remove at least a portion of a process layer formed above a substrate, a pressure sensor in contact with the substrate for sensing a change in pressure resulting from the removal of at least a portion of the process layer, and a controller
Chong Robert J.
Markle Richard J.
Advanced Micro Devices , Inc.
Vinh Lan
Williams Morgan & Amerson P.C.
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