Process compensated phase locked loop

Details Process compensated phase locked loop Process compensated phase locked loop

2002-03-12

2004-01-27

Lam, Tuan T. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S016000

Reexamination Certificate

active

06683502

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to clocking circuits for digital systems. More specifically, the present invention relates to a clocking circuit using a process compensated phase locked loop.
BACKGROUND OF THE INVENTION
Clock signals are used for a variety of purpose in digital circuits on both board level systems and integrated circuit (IC) devices, such as transceivers, field programmable gate arrays (FPGAs) and microprocessors. For example, in transceivers, clock signals are used to clock out data bits. Clock signals are typically generated using a phase locked loop (PLL).
FIG. 1
shows a conventional phase locked loop
100
used to generate a PLL output clock signal PLL_O_CLK. Phase locked loop
100
receives a reference clock signal REF_CLK having a frequency F_REF and generates a PLL output clock signal PLL_O_CLK having a frequency F_OUT, where F_OUT is equal to frequency F_REF multiplied by a multiplier, i.e. F_OUT =F_REF*M. Phase locked loop
100
comprises a phase and frequency comparator
110
, a charge pump
120
, a loop filter
130
, a voltage-controlled oscillator (VCO)
140
, and a clock divider
150
. Clock divider
150
divides PLL output clock signal PL_O_CLK to generate a feedback clock signal FBK_CLK having a frequency F_FBK equal to frequency F_OUT divided by M.
Phase and frequency comparator
110
compares the phase and frequency of feedback clock FBK_CLK to the phase and frequency of reference clock signal REF_CLK. Specifically, if an active edge of feedback clock signal FBK_CLK leads an active edge of reference clock signal REF_CLK, frequency comparator
110
causes charge pump
120
to decrease the voltage level of VCO control signal VCO_C, which is coupled to voltage-controlled oscillator
140
through loop filter
130
, to reduce frequency F_OUT of PLL output clock signal PLL_O_CLK, which is generated by voltage-controlled oscillator
140
. Conversely, if an active edge of feedback clock signal FBK_CLK is lags an active edge of reference clock signal REF_CLK, frequency comparator
110
causes charge pump
120
to increase the voltage level of VCO control signal VCO_C to increase frequency F_OUT of PLL output clock signal PLL_O_CLK. Thus, eventually, the phase and frequency of feedback clock signal FBK_CLK is nearly equal to the phase and frequency of reference clock signal REF_CLK. As explained above, frequency F_FBK of feedback clock signal FBK_CLK is approximately equal to frequency F_OUT of PLL output clock signal PLL_O_CLK divided by M, i.e., F_FBK=F_OUT/M. Thus, frequency F_OUT of PLL output clock signal PLL_O_CLK is equal to frequency F_REF of reference clock signal REF_CLK multiplied by M, i.e., F_OUT=F_REF*M. Generally, PLL output clock signal PLL_O_CLK would be provided to a clock buffer (not shown) and then distributed to the other components of the chip or system.
As explained above, phase locked loop
100
converges on the desired phase and frequency for PLL output clock signal PLL_O_CLK by controlling voltage-controlled oscillator
140
. Thus, voltage-controlled oscillator
140
must operate in a range of frequencies around the desired phase and frequency for PLL output clock signal PLL_O_CLK to compensate for such factors as operating temperature and voltage levels. However, other variable factors such as circuit frequencies and gain characteristic are dependent on process variations during the formation of phase locked loop
100
. These process dependent variable factors further increases the necessary range of operation of voltage-controlled oscillator
140
.
FIG. 2
illustrates frequency voltage curves for voltage-controlled oscillator
140
. Specifically,
FIG. 2
includes a typical frequency voltage curve
210
, a slow frequency voltage curve
220
, and a fast frequency voltage curve
230
. Typical frequency voltage curve
210
represents the typical frequency voltage response of voltage-controlled oscillator
140
. Slow frequency voltage curve
220
represents the theoretical slowest frequency response of voltage-controlled oscillator
140
based on process variations. Conversely, fast frequency voltage curve
230
represents the fastest frequency response of voltage-controlled oscillator
140
based on process variations. Because each instance of voltage-controlled oscillator
140
can have a different frequency response, voltage-controlled oscillator
140
must be designed to perform over the entire range of frequencies and voltages bounded by slow frequency voltage curve
210
and fast frequency voltage curve
230
. However, supporting such a wide range of frequency responses complicates the design and increases the cost of voltage-controlled oscillator
140
. Hence, there is a need for a method or system to reduce the process dependence of phase locked loops.
SUMMARY
Accordingly, process dependencies of phase locked loops are eliminated using the principles of the present invention. Specifically, each instance of the phase locked loop is adjusted so that the frequency voltage curve of the phase locked loop is very similar to the typical frequency voltage curve.
In accordance with one embodiment of the present invention, a phase lock loop includes a phase and frequency comparator, a charge pump, a voltage controlled oscillator, a clock divider, and a PLL process variation compensation unit. The PLL process variation compensation unit is configured to control the center frequency and the gain of the voltage controlled oscillator. Specifically, the PLL process variation compensation unit includes a center frequency control circuit and a gain control circuit.
The PLL process variation unit performs a two stage process to remove process dependency of the phase locked loop. First, the center frequency of the voltage controlled oscillator is adjusted using a biasing signal. Specifically, the control voltage of the voltage-controlled oscillator is set to zero and the divisor of the clock divider is set to a first value. Then, the bias signal is adjusted until the frequency of a feedback clock signal is approximately equal to the frequency of a reference clock signal. In the second stage, the gain of the voltage-controlled oscillator is adjusted. Specifically, the control voltage is set to a band gap reference voltage and the divisor of the clock divider is set to a second value. Then, the gain of voltage-controlled oscillator is adjusted until the frequency of the feedback clock signal is approximately equal to the frequency of the reference clock signal.


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patent: 5955928 (1999-09-01), Smith et al.
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