Process and jig for plating pin grid arrays

Details Process and jig for plating pin grid arrays Process and jig for plating pin grid arrays

1990-12-18

1992-02-11

Tufariello, T. M.

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

205122, C25D 502

Patent

active

050873318

ABSTRACT:
In a process for plating pin grid arrays (PGAs), the pins of the PGA are prebent in a prebending jig and then clipped onto a receiving jig for PGAs. At the same time, an electrical short-circuit is produced over all the pins by means of round or wedge-shaped bars or by means of metal pegs which are clamped between at least two pins. The metal pegs or bars are mounted on a metal plate arranged as far as possible at right angles to the pins. The receiving jig with a PGA mounted on it is mounted in an electrically conducting manner on an electroplating rack, connected to the cathode and immersed in an electroplating bath. After deposition of metal on the electrically conducting areas making contact with the spacing between two adjacent rows of pins on the PGA. There should be at least enough bars present to make contact with all the pins of the PGA.

REFERENCES:
patent: 3518756 (1970-07-01), Bennett
patent: 4032414 (1977-06-01), Helder

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