Process and device for phasing a local clock

Details Process and device for phasing a local clock Process and device for phasing a local clock

1980-07-25

1982-12-21

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

375110, 375111, H04J 306, H04L 704

Patent

active

043653294

ABSTRACT:
The most favorable clock signal among n available signals which present equal successive phase shifts is selected by comparison with a synchronization burst. For this, a logic phase comparison is effected between the signals obtained by division by 2 of each of the n clock phases with the bits of the synchronization burst by averaging the comparison signal obtained over several bits, and the most favorable clock phase is selected, corresponding to a phase shift close to .pi., as being the one represented by a voltage level located within a determined interval F.

REFERENCES:
patent: 3701894 (1972-10-01), Low et al.
patent: 4034352 (1977-07-01), Hotchkiss
patent: 4180701 (1979-12-01), Louth et al.

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