Process and device for managing the conflicts raised by multiple

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G06F 1300, G06F 1516

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active

044266812

ABSTRACT:
A data processing system includes at least two processors, each having a cache memory containing an index section and a memory section. A first processor performs a task by deriving internal requests for its cache memory which also may respond to an external request derived from the other processor which is simultaneously processing a task. To avoid a conflict between the simultaneous processing of an internal request and of an external request by the same cache memory, one request may act on the other by delaying its enabling or by suspending its processing from the instant at which these requests are required to operate simultaneously on the index section or the memory section of the cache memory of the processor affected by these requests. Thereby, the tasks are performed by the system at an increased speed.

REFERENCES:
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patent: 3771137 (1973-11-01), Barner et al.
patent: 4056844 (1977-11-01), Izumi
patent: 4136386 (1979-01-01), Annunziata et al.
patent: 4228503 (1980-10-01), Waite et al.
patent: 4325116 (1982-04-01), Kranz et al.
IBM Technical Disclosure Bulletin, vol. 14, No. 10, Mar. 1972, New York; R. S. Capowski et al., Multiprocessing Storage Priority Network, pp. 3141-3142.

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