Pulse or digital communications – Transceivers – Modems
Reexamination Certificate
1999-01-08
2001-07-10
Chin, Stephen (Department: 2634)
Pulse or digital communications
Transceivers
Modems
C375S372000
Reexamination Certificate
active
06259727
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and arrangements for extracting a plurality of clock signals for signal-processing circuits, especially for a digital modem, from a supplied clock signal.
BACKGROUND INFORMATION
For the digital generation and modulation of the carrier in modems, the sampling frequency f
A
in relation to the symbol frequency f
s
can be implemented in two ways. First of all, a fixed, integral ratio can be selected between the sampling frequency and the symbol frequency, so that the sampling is carried out in synchronous form. In addition, the sampling frequency must satisfy the sampling theorem, i.e. it must be greater than double as large (as a rule four times as large) as the symbol frequency. The synchronous sampling demands a is clock-pulse extraction, which extracts the sampling clock pulse from the symbol clock pulse by frequency division.
In the case of asynchronous sampling, the sampling frequency is predetermined independently of the symbol frequency. In general, the asynchronous sampling can operate with a free-running sampling clock pulse which is independent of the symbol clock pulse. In a comparison of the asynchronous with the synchronous sampling, it is significant, inter alia, that in the case of the asynchronous sampling, in spite of a variable symbol rate, a requisite anti-aliasing filter, because of the fixed sampling frequency, does not have to be designed to be variable. The asynchronous sampling requires a variable interpolation on the transmitting side and a variable decimation on the receiving side, respectively. A method for digital modulation and a digital modulator having asynchronous sampling, as well as variable interpolation and variable decimation, respectively, are described, for example, in the German Patent No. 39 19 530, and in the European Patent Application No. 0 477 131.
In such digital modems which, in addition to the actual modulator and demodulator, also contain various digital signal-processing circuits such as coders and decoders, various clock signals are needed which are adapted to the various bit rates of the signals to be transmitted between the individual circuits. In this context, the clock frequencies are only partially in a fixed, rational ratio, e.g. 48/73. To generate clock signals in such a frequency ratio, in known modems, frequency dividers and phase-comparison circuits are used which, for the most part, are realized using analog circuit technology.
The object of the present invention is to provide a method and arrangements for extracting a plurality of clock signals from a supplied clock signal, which can be implemented exclusively in digital circuit technology. At the same time, the intention is to ensure to the greatest extent possible a flexibility with regard to the symbol rate and the data rate.
SUMMARY OF THE INVENTION
This objective is fulfilled according to the present invention, in that the clock signals to be extracted are in each case formed from an output signal of an accumulator of predefined bit width n, the accumulator in each case accumulating an increment in the clock pulse of the supplied clock signal and, in the process, performing a modulo2
n
operation.
The method of the present invention can also be used in other signal-processing circuits than digital modems. To adapt a digital modem to the symbol rates required at any one time, the predefined value can in each case be programmed. To carry out the method, a special digital hardware is suitable which can be beneficially implemented, from the standpoint of outlay, in an FPGA (Field Programmable Gate Array) or in an ASIC (Application Specific Integrated Circuit).
However, particularly in the case of digital modems having asynchronous sampling, the problem arises that a second clock signal is supplied, namely a clock pulse that is rigidly coupled to the symbol clock pulse, but is not coupled to the supplied first clock signal. In order to avoid an error propagation in the form of clock-pulse slips resulting from this, in a further development of the method according to the present invention, a second clock signal is supplied, and the increment is changed as a function of the phase position of the second supplied clock signal in relation to one of the clock signals to be extracted.
This change can be carried out continuously or quasi continuously. However, to reduce the computing expenditure, in each case a plurality of predefined values for the increment can be stored in a memory, one of these values being selected, as a function of the phase position, as the increment to be accumulated. In this context, an adequate control response exists for many application cases if the increment to be accumulated is selected from three predefined values. In addition, a time adaptation of the three points of this three-step control is effected, in that there is a common divisor, and the three increments are free of remainders. Which specific embodiment of this further development is selected depends essentially on the respective demands for freedom from jitter.
It may be that this further development does not obviate a residual jitter of the extracted clock signals. However, this is generally not disturbing for the applications of the method according to the invention taken into consideration. Because of the generally relatively constant frequencies of the first and the second supplied clock signal, it is sufficient for this further development if the three predefined values differ from each other by, in each case, approximately 0.5%. In addition, this further development makes it possible for the predefined values to differ insignificantly from the theoretical values which result from the frequency ratios, so that the accuracy or the number of binary positions in the accumulators can be limited to practicable values.
To avoid the aforesaid error propagation, if the increment supplied at any one time to an accumulator is not remainder-free, provision can be made in the method of the present invention that a further accumulator having a predefined bit width m and a numerical range, capable of representation, of Z actual element of [2
m
-1.0], accumulates remainder values in the clock pulse of the first supplied clock signal, and that the respective content of the further accumulator, after modulo2
m
formation, is supplied to a carry-over input of the accumulator for the clock signal to be extracted in each case.
However, error propagation is also avoided if the increment supplied in each case to an accumulator is divisible, so as to be remainder-free, in the numerical range that is representable by the predefined bit width, by the largest common divisor of all the clock-pulse conversion ratios to be implemented.
Another embodiment of the method of the present invention is that at least one of the clock signals to be extracted is formed from the overflow of the respective accumulator. However, in this case, it is necessary to put up with a certain remainder jitter.
Another embodiment of the method of the present invention permits jitter-free extraction of the clock signal to be extracted, in that at least one of the clock signals to be extracted is generated by sinusoidal formation of the accumulator content, digital/analog conversion, and zero-crossing detection.
The present invention also provides an arrangement for extracting clock signals in a digital modem, a digital signal to be transmitted being supplied via a plurality of signal-processing circuits, particularly coders, and via an intermediate memory, to a device for variable interpolation, from which a modulated carrier having a first supplied clock signal is able to be read out, and a second supplied clock signal being extracted from the digital signal, provision being made that, for the signal-processing circuits and for the readout process from the intermediate memory, clock signals are extracted in each case from an accumulator of a predefined bit width, the accumulator accumulating an increment in the clock pulse of the first supplied clock sign
Al-Beshrawi Tony
Bobert Bosch GmbH
Chin Stephen
Kenyon & Kenyon
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