Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-02-26
2001-03-13
Hjerpe, Richard A. (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S060000, C345S182000, C345S182000
Reexamination Certificate
active
06201519
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to an addressing process and device for plasma panels and in particular to a grey level coding process.
BACKGROUND OF THE INVENTION
On plasma screens, the grey level is not produced in a conventional manner using amplitude modulation of the signal but rather temporal modulation of this signal, by exciting the corresponding pixel for a greater or lesser time depending on the level desired. It is the phenomenon of integration by the eye which makes it possible to render this grey level. This integration is performed during the frame scan time.
The eye actually integrates much faster than the frame duration and is therefore liable to perceive, in cases of particular transition of the addressing bits, variations in level which do not reflect reality. Contour defects or “contouring” as it is known, may thus appear in the moving images. These defects may be compared to poor temporal restitution of the grey level. More generally, false colours appear on the contours of objects, each of the cells of a colour component possibly being subject to this phenomenon. This phenomenon is even more harmful when it occurs in relatively homogeneous zones.
A simple theoretical solution for limiting these problems of the appearance of false contours is to multiply the number of sub-scans so that the disturbances related to the modifications of the video level from one frame to another are made minimal. Such a solution has formed the subject of a patent application in France filed by the Applicant on Apr. 25, 1997 under national registration number 97 05166. By virtue of the simultaneous addressing of two consecutive lines in respect of bits of the column addressing word and by virtue of the sub-scans thus saved, allowing transcoding of the column control words over a greater number of bits, it is possible to reduce the weights of the most significant bits.
The losses of resolution which are caused by this may be limited by using the redundancy possibilities of the codes for the recoding of the grey level. However, it is not possible to curb the magnitude of these losses of resolution.
The purpose of the invention is to alleviate the aforesaid drawbacks.
SUMMARY OF THE INVENTION
Its subject is a process for addressing cells arranged as a matrix array, each cell being situated at the intersection of a line and a column, the array having line inputs and column inputs for displaying grey levels NG defined by video words making up a digital video signal, the column is inputs receiving control words for this column, each bit of a control word triggering or not triggering, depending on its state, the selection of the cell of the addressed line and of the corresponding column for a time proportional to the weight of this bit within the word, characterized in that it consists:
in splitting up the grey levels NG1, NG2, . . . , NGn relating to an information item regarding the luminance of n cells situated in the same column and in consecutive lines I+1 to I+n into at least one control word corresponding to a value common to the n lines, VC, and into n control words corresponding to values specific to each line, VS1 to VSn, such that, i varying from 1 to n:
NGi=VSi+VC,
in transmitting the bits of the control word corresponding to the common value VC on the column inputs by simultaneously addressing the n lines I+1 to I+n in respect of the selection of the corresponding cells.
According to a mode of implementation of the process, the specific values VS1 and VS2 possess a common part equal to a predetermined percentage of the lowest grey level.
The subject of the invention is also a device for implementing this process comprising a video processing circuit for processing the video data received, a video memory for storing the processed data, the video memory being linked to column drivers in order to control the column addressing of the plasma panel on the basis of column control words, a control circuit for the line drivers, characterized in that the processing circuit comprises means for calculating specific values and a common value for video data relating to at least two consecutive lines and in that the control circuit of the line drivers simultaneously selects these consecutive lines during the transmission by the column drivers of the bits of the column control words corresponding to the common values.
According to a particular embodiment of the device, the processing circuit also comprises means for coding the specific values in increments of 5 and for calculating a common value minimizing the global coding error corresponding to the difference between the sum of the values to be coded and the sum of the values coded on the basis of this common value, the value calculated being, when several choices are possible, that which makes it possible to distribute the resulting global error over each of the values to be coded.
The subject of the invention is also a process for addressing cells arranged as a matrix array, each cell being situated at the intersection of a line and a column, the array having line inputs and column inputs for displaying grey levels NG defined by video words making up a digital video signal, the column inputs receiving control words for this column, each bit of a control word triggering or not triggering, depending on its state, the selection of the cell of the addressed line and of the corresponding column for a time proportional to the weight of this bit within the word, characterized in that it consists
in coding the grey levels NG1 and NG2 relating to an item of information regarding the luminance of two cells situated in the same column and in two adjacent lines I and I+1 as a first control word corresponding to a common value VC and as a second and third control word corresponding to specific values, VS1 and VS2, such that:
NG1=VS1+VC
NG2=VS2+VC
in transmitting the bits of the first control word on the column inputs by simultaneously addressing the two lines I and I+1 in respect of the selection of the corresponding cells.
According to a particular mode of implementation of the process, when the coding of the specific values is carried out in an increment different from unity, the common value VC is chosen in such a way as to distribute the resulting error over each of the specific values.
According to a particular mode of implementation of the process, at least one of the weights of the word corresponding to the common value and/or to the specific value is different from a power of two.
According to a particular mode of implementation of the process, the weights of the words for coding the specific value and/or the common value are determined in such a way that identical values to be coded can correspond to different coding words.
According to a particular mode of implementation of the process, when several choices of coding exist, the words chosen are those possessing the lowest high-order bits.
Likewise, according to a particular mode of implementation of the first process described above, the specific control words are themselves split up into control words common to two or more successive lines and these lines are selected during the transmission of these common control words.
The process for coding a grey level of a pixel (or of a cell) is carried out by separation of the information item to be transmitted between a value specific to the pixel to be coded and a value common to this pixel and to the pixel of the adjacent line and same column.
By virtue of the invention, the loss of resolution is curbed. Implementation is simple, making it possible to limit the cost of setup.
REFERENCES:
patent: 5475448 (1995-12-01), Saegusa
patent: 5848198 (1998-12-01), Penn
patent: 5999154 (1999-12-01), Yoshioka
patent: 6091380 (2000-07-01), Hashimoto et al.
patent: 0762373 (1997-03-01), None
patent: 8-248916 (1996-09-01), None
“Vertical Reference Coding For Digital Gray Level Images”, IBM Technical Disclosure Bulletin, Dec. 1979, vol. 22, Issue 7, pp. 2980-2985.
Chevet Jean-Claude
Doyen Didier
Touchais Dominique
Eisen Alexander
Fried Harvey D.
Henig Sammy S.
Hjerpe Richard A.
Thomson Multimedia
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