Process and circuit for the demodulation of chrominance signals

Details Process and circuit for the demodulation of chrominance signals Process and circuit for the demodulation of chrominance signals

1984-12-06

1987-02-17

Masinick, Michael A.

Facsimile and static presentation processing

Static presentation processing

Attribute control

358 24, H04N 5455, H04N 966

Patent

active

046443886

ABSTRACT:
The present invention relates to chrominance decoding circuits and more particularly to a novel circuit for demodulating chrominance signals, B-Y or R-Y. This circuit comprises, connected in series, a multiplier multiplying the U or V-modulated chrominance signal by itself, a filter giving at the output the square (B-Y).sup.2 or (R-Y).sup.2 of the chrominance signal, a device for extracting the square root giving an absolute value .tbd.B-Y.tbd. or .tbd.R-Y.tbd. of the chrominance signal, and a multiplier multiplying said absolute value by the sign of the chrominance signal B-Y or R-Y to obtain at the output said chrominance signal, B-Y or R-Y.

REFERENCES:
Funkschau, vol. 43, No. 13, ler juillet 1971, pp. 409-412, Munchen, DE; M. F. Koubek: "Pal-Decoder ohne Laufzeitleitung" *p. 411, colonne de gauche, lignes 4-18*.

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