Process and circuit arrangement for checking a program in data p

Details Process and circuit arrangement for checking a program in data p Process and circuit arrangement for checking a program in data p

1985-02-06

1987-04-07

Atkinson, Charles E.

Excavating

371 51, G06F 1110

Patent

active

046566317

ABSTRACT:
In checking a program in data processing units, the working memory, before the completion of the program, has written into it information to which respectively a false parity signal is assigned. In this way program mistakes in the program to be checked, which can be revealed in a read access to a non-normalized memory cell, are recognized instantly.

REFERENCES:
patent: 3257546 (1966-06-01), McGovern
patent: 3465132 (1969-09-01), Crockett et al.
patent: 3491337 (1970-01-01), Guzak, Jr. et al.
patent: 3786415 (1974-01-01), Phillips et al.
patent: 4355393 (1982-10-01), Kubo et al.
Kobesky, Diagnostic Parity Error Forcing Mechanism, IBM Technical Disclosure Bulletin, vol. 19, No. 3, Aug. 1976, p. 853.

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