Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2002-05-08
2004-06-15
Le, Dung (Department: 2818)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S113000, C438S114000, C216S017000, C156S345420
Reexamination Certificate
active
06750118
ABSTRACT:
BACKGROUND
This invention pertains to a process and an apparatus to subdivide objects, in particular to produce wafers from semi-conducting, monocrystalline blocks, wherein these blocks are subdivided into slices with the help of at least one cutting tool and under the influence of an etchant.
The apparatus has a cutter arrangement that has at least one cutting tool and an etchant feed device.
In the solar cell and chip industry, very thin wafers are necessary that have very good electronic properties. Current manufacturing processes deal with the mechanical abrading of an object to be cut containing the monocrystalline block (ingot). What is most commonly used for this is the so-called multi-wire slurry saw (MWSS). This mechanical process results in high surface damages to the silicon, making subsequent etching and cleaning steps necessary, and can lead to increased breaks. In addition, the saw losses are high and the minimum attainable wafer thickness is limited to approximately 200 &mgr;m.
Another so-called “stream etching” process is known in which a taut wire is used as the cutting tool. Etchant flows along this wire. The wire and the block to be subdivided are connected to a current source so that the cutting process occurs in a non-contact fashion through electrochemical etching. This process results in wafers with planar, practically undamaged surfaces, with the breakage rate and the cutting losses being minimized, and allowing the manufacture of very thin wafers. The problem with this process is that these thin wafers can stick together by adhesion, making it very difficult to separate them.
SUMMARY
The object of this invention is to provide a process and an apparatus that allows very thin wafers or similar sliced objects to be manufactured while safely and reliably separating them.
To accomplish this object, the process according to the invention proposes to introduce into each slit cut a foil to separate the slices prior to the object (ingot) being completely cut and subdivided into individual slices. It is suggested that the apparatus used for this purpose be provided with one or more foils to be introduced into the respective slit cut, which is produced by the cutting tool or cutting tools, between adjacent slices in the object to be subdivided. These foils are then used to separate the adjacent slices.
This efficiently prevents the resultant wafers from sticking together. The individual separation of the wafers is performed right when the cutting process is performed so that the necessary number of process steps in the manufacturing of silicon wafers is reduced.
It is advantageous for the apparatus to have a foil carrier for one or more separating foils to separate adjacent slices. This carrier has a device to hold the separating foil(s) taught inside the slits cut.
If a foil carrier is provided for a number of adjacent parallel foils, it is preferable to also have an adjustable distance maintainer.
This allows the precise setting and adjustment of the parallelness of the foils if a number of wafers are produced at the same time.
The separating foil(s) are formed, in particular, of a material that is resistant to the etchant used, the temperature present during the process as well as any existing electrical potentials.
It is preferred that the separating foil be made of polytetrafluoroethylene (PTFE).
For the electrochemical cutting of silicon using potassium hydroxide, thin PTFE foils are particularly well suited since they have a very low coefficient of friction, are not wetted by potassium hydroxide and are resistant to potassium hydroxide.
In order to ensure an improved mechanical separation of electrolyte and foils, the separating foil can have at least one exterior side with a profiled or structured surface, in particular with a microstructured surface. If necessary, it can have a reticular structure.
Additional embodiments of the invention are discussed below.
REFERENCES:
patent: 6284661 (2001-09-01), Yokoyama et al.
“A New Route Towards 50 &mgr;m Thin Crystalline Silicon Wafer Solar Cells,” Willeke, Gerhard and Kray, Daniel; Paper VCI.57, 17th EU-PVSEC Conference (Oct. 22, 2001).
Kray Daniel
Willeke Gerhard
Fraunhofer-Gesellschaft zur Forderung der ange-wandten Forschung
Le Dung
Volpe and Koenig P.C.
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