Optics: measuring and testing – By alignment in lateral direction
Reexamination Certificate
2001-03-02
2003-12-23
Smith, Zandra V. (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
C356S401000, C356S614000, C430S022000, C430S030000
Reexamination Certificate
active
06667806
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process for manufacturing a semiconductor device and in particular to a method and apparatus for detecting and correcting the alignment error at a high precision in an exposure step and a process for manufacturing a semiconductor device based upon a result of the correction of the alignment error.
The process for manufacturing a semiconductor device is conducted by repeating on each layer the steps of forming a layer on a wafer; applying a photoresist which is a photosensitive agent upon the formed layer; exposing the resist with a circuit pattern on a reticle and developing it; and then forming the circuit pattern on the wafer by etching away the layer. If there is a difference of the position of the circuit pattern on exposure relative to an underlaying layer pattern in this manufacturing process, the circuit may then be broken or short-circuited, resulting in an defective semiconductor device. Accordingly, the relative difference in position between a registering mark which is formed of the resist after the development and an alignment mark on the underlaying layer is automatically measured by means of an optical microscope and the difference in position is fed back to an exposure apparatus at subsequent exposing step. The alignment mark is usually provided in a region at the edge of an exposure area in which no circuit pattern is provided. The alignment mark is formed at a line width of 2 to 4 &mgr;m, which is larger in comparison with the circuit line width so that it can be resolved by an optical detecting method.
The present inventors have found that following problems which have not heretofore been considered will occur since a tolerable error in alignment is about 30 nm for DRAMs having a line width of 0.1 &mgr;m which will be developed in the future.
A first problem resides in an error of writing using a reticle. The pattern on the reticle is scanned by means of an electron beam scanning apparatus. The error in position of scanning is about 50 nm on the reticle. In case of ⅕ scaled down exposure, the error is about 10 nm on the wafer, which is not negligible for the tolerable error of 30 nm.
Accordingly, the shift of the alignment mark at the edge of the exposure area does not necessarily match with that of the circuit at the exposure area.
A second problem resides in the distortion of a projecting lens of the exposure apparatus. Since the image of the reticle which is transferred upon the wafer by means of the projecting lens also has a distortion of about 10 nm, this also causes the mismatch of the alignment error of the alignment mark with the circuit.
In order to overcome these problems, it is necessary to measure the alignment error by measuring the circuit pattern per se rather than the alignment mark. At this time, it is difficult to resolve the circuit pattern having a width of 0.1 &mgr;m by using a prior art optical microscope. At this end, a method of measuring the alignment mark on the circuit area by using an SEM (scanning electron microscope) after etching is disclosed in, for example, SPIE, Vol. 3677, pp 239 to 247, 1999. This method is conducted by measuring the distance between the contour of a connection hole and the edge of the underlaying wiring pattern at the bottom of the hole, between the wiring layers.
However, only the surface contour can be detected since SEM conducts the image detection relying upon the amount of the secondary electrons which are generated on the surface of an object to be observed. In other words, if the underlaying layer wiring pattern is larger than the diameter of the connection hole, it would be difficult to measure the alignment error by means of the SEF since the edge of the wiring patterns then could not be detected from the bottom of the hole.
SUMMARY OF THE INVENTION
The present invention provides a process for measuring the alignment error at the step for exposing a semiconductor with light in which the underlaying layer pattern is not exposed on the surface in the circuit area. Novel features and advantages will be apparent from the following description and the annexed drawings.
In accordance with the present invention, a process for manufacturing a semiconductor device comprises the steps of:
(1) forming a first pattern on a substrate;
(2) forming a second pattern on said first pattern;
(3) detecting a first image by irradiating said substrate on which said first and second patterns are formed, with illuminating light having a first wavelength;
(4) detecting a second image by irradiating said substrate on which said first and second patterns are formed, with illuminating light having a second wavelength;
(5) calculating the relative positional difference between said first and second images;
(6) preliminarily determining the relationship between the relative positional difference between the first and second images and the positional difference of said second pattern relative to said first pattern;
(7) inputting the relative positional difference between said first and second images into the said relationship;
(8) calculating the positional difference of said second pattern relative to said first pattern;
(9) feeding back said calculated positional difference to an exposing apparatus for forming said second pattern in next process as a correction value; and
(10) forming the second pattern, the positional difference of which is corrected by exposing a second pattern by means of exposing apparatus using the fed back correction value.
This makes it possible to measure the positional difference of the second pattern having a size which is less than the limit of the optical resolution relative to the first pattern. Accordingly, the alignment error in the circuit area including the error due to the influences of the lens distortion and the reticle writing error can be determined, so that high accurate correction for the exposing apparatus can be conducted.
The process for manufacturing a semiconductor device is characterized in that light which is detected at the steps for detecting said first and second images is polarized in a direction parallel with the longitudinal directions of said first and second patterns.
Since this makes it possible to detect said first and second images at high contrast, measuring the alignment error at high accuracy can be carried.
The process for manufacturing a semiconductor device is characterized in that said first and second patterns are a plurality of patterns having the same pitch.
It is possible to detect the images of a plurality of patterns in which the relative positional differences between the first and second patterns are equal. Accordingly, measuring the alignment error at high accuracy in which the influence of the local deformation of the pattern is small can be achieved.
The process for manufacturing a semiconductor device is characterized in that said step for calculating the relative positional difference between said first and second images calculates the phase at a frequency corresponding to the maximum spectrum which is obtained by Fourier-transforming the images of said plurality of patterns in a direction in which said plurality of patterns are arrayed so that the relative positional difference is calculated from the calculated phase.
The average relative positional error between said first and second patterns in said plurality of patterns can be achieved at high speed and high accuracy.
These and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
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Kato Takeshi
Nakata Toshihiko
Yoshitake Yasuhiro
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Smith Zandra V.
Stock Gordon J
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