Process and apparatus for finite field multiplication (FFM)

Details Process and apparatus for finite field multiplication (FFM) Process and apparatus for finite field multiplication (FFM)

2006-02-21

2006-02-21

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07003538

ABSTRACT:
Finite field multiplication of first and second Galois elements having n bit places and belonging to a Galois field GF 2ndescribed by an irreducible polynomial is performed by forming an intermediate result Z of intermediate sums of partial products of bit width 2n−2 in an addition part of a Galois multiplier. The intermediate result Z is processed in a reduction part of a Galois multiplier by modulo dividing by the irreducible polynomial, whereby after all XOR's are traversed a result E with n bits is computed.

REFERENCES:
patent: 4697248 (1987-09-01), Shirota
patent: 4918638 (1990-04-01), Matsumoto et al.
patent: 5046037 (1991-09-01), Cognault et al.
patent: 6343305 (2002-01-01), Ko.cedilla. et al.

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