Communications: electrical – Land vehicle alarms or indicators – Internal alarm or indicator responsive to a condition of the...
Patent
1996-08-08
1998-02-03
Barry, Esq., Lance Leonardo
Communications: electrical
Land vehicle alarms or indicators
Internal alarm or indicator responsive to a condition of the...
34082552, 370445, 370447, 39520006, 395856, 395299, 3642292, 3642304, 36424292, G06F 1300
Patent
active
057154074
ABSTRACT:
A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of the device receiver and decrease the overall latency on the bus is provided. In the preferred embodiment the request packet is transmitted on ten The packet is transmitted over six sequential bus cycles, wherein during each bus cycle, a different portion of the packet is transmitted. The lower order address bits are moved ahead of the higher order address bits of the memory request. This enables the receiving device to process the memory request faster as the locality of the memory reference with respect to previous references can be immediately determined and page mode accesses on the DRAM can be initiated as quickly as possible. The type of memory access is arranged over a plurality of clock cycles, placing the more critical bits first. The count of blocks of data requested is arranged to minimize the number of bit positions in the packet used and therefore the number of transmission lines of the bus and the number of bus receiver contacts on the receiving device.
REFERENCES:
patent: 4247817 (1981-01-01), Heller
patent: 4481625 (1984-11-01), Roberts et al.
patent: 4519034 (1985-05-01), Smith et al.
patent: 4523274 (1985-06-01), Fukunaga et al.
patent: 4539677 (1985-09-01), Lo
patent: 4630264 (1986-12-01), Wah et al.
patent: 4658250 (1987-04-01), Nering et al.
patent: 4701909 (1987-10-01), Kavehrad et al.
patent: 4751701 (1988-06-01), Roos et al.
patent: 4785396 (1988-11-01), Murphy et al.
patent: 4809264 (1989-02-01), Abraham et al.
patent: 4811202 (1989-03-01), Schabowski
patent: 4845663 (1989-07-01), Brown et al.
patent: 4860198 (1989-08-01), Takenaka
patent: 4912627 (1990-03-01), Ashrin et al.
patent: 4929940 (1990-05-01), Franaszek et al.
patent: 4959829 (1990-09-01), Griesing
patent: 5012467 (1991-04-01), Crane
patent: 5048009 (1991-09-01), Conrad
patent: 5063612 (1991-11-01), McKeown
patent: 5124982 (1992-06-01), Kaku
patent: 5272700 (1993-12-01), Hansen et al.
patent: 5301303 (1994-04-01), Abraham et al.
patent: 5311172 (1994-05-01), Sadamuri
patent: 5319755 (1994-06-01), Farmwald et al.
patent: 5339307 (1994-08-01), Curtis
patent: 5383185 (1995-01-01), Armbruster et al.
patent: 5408129 (1995-04-01), Farmwald et al.
patent: 5544322 (1996-08-01), Chen
patent: 5564025 (1996-10-01), De Freese et al.
patent: 5606717 (1997-02-01), Farmwald et al.
Gumm, Steve L. and Carl T. Dreher, Unraveling the Intricacies of Dynamic RAMs, Electronic Design News, pp. 155-165 (Mar. 30, 1989).
James Martin et al., "Local Area Networks Architectures and Implementations", pp. 87, 223-224 (1989).
Martin, J. "Local Area Networks: Architectures and Implementanous (USA, Prentice-Hall 1989)", pp. 33, 84-88.
Barth Richard Maurice
Griffin Matthew Murdy
Horowitz Mark Alan
Ware Frederick Abbott
Barry, Esq. Lance Leonardo
Rambus Inc.
LandOfFree
Process and apparatus for collision detection on a parallel bus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process and apparatus for collision detection on a parallel bus , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process and apparatus for collision detection on a parallel bus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-670855