Procedure and data structure for synthesis and transformation of

Boots – shoes – and leggings

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364488, 395921, G06F 1560

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052126501

ABSTRACT:
A procedure is described for the synthesis and transformation of a logic circuit design, provided by the designers, into a database capable of being used to fabricate the actual circuit. The procedure involves the use of model instances which represent the use of circuit components. The original model instances can be associated with groups of rules that determine resulting configurations of generally different model instances or groups of model instances. The rules are tested and, in the presence of a `true` result, a new model instance (or model instances) can replace one or more original model instances in the data base. The rules associated with a model type (or definition) are rules derived by a design model engineer and can include coupled model instances. The rules can be associated with model definitions, as well as model instances. The data structures associated with each model instance indicate the model interface as well as the model interface port and permit a path to followed in the circuit in either the forward or the reverse signal direction. The model instances reside within model definitions which reside with design data in hierarchical form. The rules controlling the synthesis and transformation of the circuit are contained in a separate hierarchy of data structures or knowledge structures to which reference can be made by design data structures.

REFERENCES:
patent: T935003 (1975-06-01), Linville et al.
patent: 4377849 (1983-03-01), Finger et al.
patent: 4386403 (1983-05-01), Hsieh et al.
patent: 4510616 (1985-04-01), Lougheed et al.
patent: 4554631 (1985-11-01), Reddington
patent: 4584653 (1986-04-01), Chih et al.
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4656603 (1987-04-01), Dunn
patent: 4700317 (1987-10-01), Watanabe et al.
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4937755 (1990-06-01), Yokota et al.
C. L. Forgy, "OPS5 User's Manual," Carnegie-Mellon University (Jul., 1981).
H. Brown et al., "Palladio: An Exploratory Environment for Circuit Design," Computer, vol. 16, No. 12, pp. 41-56 (Dec. 1983).
Saito et al., "A CAD System for Logic Design Based on Frames and Demons," Fujitsu Scientific and Technical Journal, vol. 18, No. 3, pp. 437-451 (Sep., 1982).
Darringer et al., "Logic Synthesis Through Local Transformations," IBM Res. Develop., vol. 25, No. 4, pp. 272-280 (Jul., 1991).
"Artificial Intelligence in Computer Aided Design" by Shi Jiaoying et al., Computers in industry, Elseivier Science Publishers B.V. (North-Holland), 1987, pp. 277-282.
"Diverse design tools break into logic-synthesis arena", Computer Design, Oct. 15, 1987, pp. 20-21.
"Incremented Logic Synthesis Through Gate Logic Structure Identification" by T. Shinsha et al., 23rd Design Automation Conf., IEEE 1986, pp. 391-397.
Randy H. Katz, `Managing the Chip Design Database`, IEEE Computer, vol. 16, No. 12, Dec. 1983, pp. 26-35.
"Quality of Designs from an automatic Logic generation (ALERT)", Friedman et al., 7th DA Conference 1970, pp. 71-89.
"LORES-Logic Reorganization System", Nakamura et al., 15th DA Conference 1978, pp. 250-260.
"A New Look at Logic Synthesis", Darringer et al., 17th DA Conference 1980, pp. 543-549.
"Methods Used in an Automatic Logic Design Generator (ALERT)", Friedman et al., IEEE-Computer, vol. C-18, No. 7, Jul. 1969, pp. 593-610.
D. L. Dietmeyer, "Logic Design of Digital Systems", Allynt Bacon, Boston, 1978, pp. 156-238.
Daniel et al., "CAD Systems for IC Design", IEEE, Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-1, No. 1, Jan. 1982, pp. 2-11.
Trimberger, "Automating Chip Layout", IEEE, Spectrum, vol. 19, No. 6, Jun. 1982, pp. 38-45.
Franco et al., "The Cell Design System", IEEE, 18th Design Automation Conference, paper 12.4, 1981, pp. 240-247.
Kessler et al., "Standard Cell VLSI Design: A Tutorial", IEEE Circuit and Devices Magazine, Jan. 1985, pp. 17-34.

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