Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-08-21
2004-02-03
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754120, C324S765010, C324S762010
Reexamination Certificate
active
06686753
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analysis prober and an analysis apparatus for analyzing a semiconductor chip, and more particularly to a prober for semiconductor chip analysis and an analysis apparatus for optically evaluating a semiconductor chip.
2. Description of the Related Art
Methods of performing evaluation and analysis of semiconductor devices include an EMS (Emission Microscope) method in which, while a voltage is applied to a semiconductor device, an optical detector observes light emitted from a faulty point or the like, and an OBIC (Optical Beam Induced Current) method in which a surface of a semiconductor chip is scanned with laser light to detect a change in current produced at a faulty point or the like.
FIG. 1
is a sectional view showing a prior art of a wafer analysis apparatus which performs evaluation and analysis of such a kind for a semiconductor device in a wafer state.
Optical device
11
for analysis such as a CCD (Charge Coupled Device) camera or laser is disposed at an upper position, and semiconductor wafer
13
is placed with its front facing upward on wafer stage
12
. Wafer stage
12
is moved for positional adjustment such that a chip to be analyzed is located directly below optical device
11
for analysis. Semiconductor wafer
13
is vacuum absorbed by and fixed to wafer stage
12
which has numerous small holes therein for allowing vacuum absorption. Then, while the surface of the wafer is viewed from above using microscope
14
for probe position check, the position of probe
6
(metallic probe) is set through the following operations to perform probing. Specifically, probe
6
is moved vertically by manipulating adjustment handle
24
a
of manipulator
5
fixed to platen
15
, and is moved along the surface of the semiconductor wafer by manipulating adjustment handle
24
b.
After such probing, electrical input is provided to an integrated circuit within the semiconductor chip through probe
6
, and optical device
11
for analysis is used from above to detect light produced from a faulty point or the like or to scan the surface of the semiconductor chip with a laser beam. Simultaneously with the observation of the light, optical device
11
for analysis observes the image of the surface of the chip to be analyzed to identify the point where the light is produced or the point where a current change is produced, thereby performing evaluation and analysis of the chip to be analyzed.
As described above, in typical analysis with probing, all the optical detection, scanning and probing are performed on the front of the chip.
It should be noted that microscope
14
for probe position check and optical device
11
for analysis may be installed as one unit having both functions.
In recent years, however, wiring is increasingly multilayered with a larger scale semiconductor integrated circuit, which makes it difficult to identify a faulty point from the front of a chip which is covered with metallic wiring. As a technique to analyze a fault in such an integrated circuit, a technique of detecting a defective point from the back of a chip (back side analysis technique) is conducted with the EMS method or OBIC method by utilizing infrared light with high transmittance for a semiconductor.
The back side analysis technique which can utilize only the light in the infrared range, however, has problems such as lower detection sensitivity than that of the analysis from the front of a chip which can utilize a wider wavelength range, and in some cases, the front side analysis technique may be more effective. From the need for addressing such a condition, a number of commercially available apparatuses are capable of evaluation and analysis from both front and back of a chip.
Such analysis apparatuses require that electrical input is supplied to the front of a semiconductor chip having an integrated circuit formed therein, and the semiconductor chip is held in such a manner that optical observation is allowed from the back of the chip at back side analysis, or from the front of the chip at front side analysis. To this end, such analysis apparatuses generally employ an approach in which an expensive optical device for analysis responsible for the function of detecting a defective point is set to one system, and the semiconductor chip is held with its front and back reversed depending on whether the front side analysis or back side analysis is performed.
For example, a semiconductor chip is mounted in a mold package or the like which is processed with relative ease, and the chip is opened at the back for the back side analysis technique while the chip is opened at the front for the front technique, thereby allowing both analysis techniques to be performed with relative ease. Specifically, even when the whole package is held with its front and back reversed, input/output terminals of the integrated circuit are drawn to lead terminals around the package to enable electrical input through the lead terminals. In this case, however, there is a problem of a longer analysis TAT (Turn Around Time) due to the time taken for the mounting into and opening of the package.
FIG. 2
is a sectional view of a mold package for explaining the back side analysis technique. Semiconductor chip
4
is mounted on island
16
and wire bonding is performed to connect input/output terminals of an integrated circuit to lead
17
. Semiconductor chip
4
and bonding wire
18
are held with mold resin
19
. Then, mold resin
19
and island
16
on the back of the chip are removed to provide opening
20
for exposing the back of the chip. In an analysis apparatus having a package accommodating mechanism, electrical input/output is made from lead
17
and back side analysis is performed through back opening
20
.
On the other hand, when analysis is performed on a chip which is not mounted in a package or in a wafer state, probing is required for electrical input. In this case, if the chip is turned upside down, the probing is performed from the opposite direction, which change is not easy.
FIG. 3
is a sectional view of an analysis apparatus which has optical device
11
disposed at an upper position and is configured to allow probing of a semiconductor wafer from both above and below, but in this case probing is performed from below for back side analysis. Semiconductor wafer
13
is placed such that a chip to be analyzed is disposed directly below opening
22
for analysis formed at the center of removable wafer stage
21
, and the wafer is fixed with vacuum absorption using numerous holes formed in a contact surface of removable wafer stage
21
. Thereafter, removable wafer stage
21
is set on a wafer stage mounting section (not shown) provided in the analysis apparatus such that the back of the chip faces upward. While the surface of the wafer is viewed from below with CCD camera
23
for probe position check, probing is performed by manipulating adjustment handles
24
a
,
24
b
of manipulator
5
provided at platen
15
similarly to the aforementioned prior art. Electrical input is supplied to an integrated circuit within the semiconductor chip through probe
6
, and the back side analysis is performed from the aforementioned opening
22
using optical device
11
for analysis.
When front side analysis is performed using the analysis apparatus, manipulator
5
is mounted to platen
15
on the opposite side and removable wafer stage
21
and CCD camera
23
are removed. A wafer stage for front side analysis is disposed in a lower position and a semiconductor wafer is fixed thereon, and then probing and the front side analysis are performed from above with optical device
11
for analysis which is integrated with a microscope.
A first problem in the aforementioned cases is a long analysis TAT when a semiconductor chip is mounted in a package for analysis. In the back side analysis, the analysis TAT is particularly longer. That is because it is necessary that the semiconductor chip is mounted in the package for allowing electrical in
Karlsen Ernest
NEC Electronics Corporation
Young & Thompson
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