Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-10-19
2003-02-11
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06518779
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a probe card for use in simultaneously testing, at a wafer level, plural integrated circuits of chips formed on a semiconductor wafer.
In accordance with recent remarkable development in decrease in size and price of electric equipment mounting semiconductor integrated circuit devices, there are increasing demands for further decrease in size and price of the semiconductor integrated circuit devices.
In general, a semiconductor integrated circuit device is supplied with a semiconductor chip and lead frames electrically connected through bonding wires and the semiconductor chip sealed with a resin or ceramic, so as to be mounted on a printed substrate.
Now, a conventional burn-in apparatus used for a burn-in test of resin sealed semiconductor chips will be described with reference to an accompanying drawing.
FIG. 5
is a schematic diagram for showing the structure of the conventional burn-in apparatus. The burn-in apparatus
100
of
FIG. 5
includes a burn-in chamber
101
and a pattern generator (PG)
121
for generating a test signal to be input to an integrated circuit on a semiconductor chip.
Within the burn-in chamber
101
, plural burn-in (BI) boards
102
are held and connected with connectors
103
. Herein, merely two BI boards
102
are shown, but more BI boards are contained in the burn-in chamber
101
with a vertical interval therebetween. On each of the BI boards
102
, a large number of resin sealed semiconductor chips
104
are placed in an input enable state.
At the outside of the burn-in chamber
101
between a signal line
122
connected with the PG
121
and the BI boards
102
, driver boards
123
respectively corresponding to the BI boards
102
are held and connected with outer portions of the connectors
103
.
On each of the driver boards
123
, plural active devices
124
, such as a driver for driving a test signal from the PG
121
and a comparator for comparing an expected value signal to each semiconductor chip
104
on the BI boards
102
and an output signal thereof and outputting a signal obtained through the comparison to the PG
121
, are placed.
On the other hand, as is described in U.S. patent application Ser. No. 08/358,609 and “A Wafer-Level Burn-in Technology Using the Contactor Controlled Thermal Expansion” (Y. Nakata et al., Proceedings 1997, International Conference and Exhibition on Multichip Models, pp. 259-264, April 1997), a probe card for simultaneously conducting the burn-in on semiconductor chips at the wafer level in a batch has been proposed.
FIG. 6
is a sectional view of the proposed probe card for batch burn-in (hereinafter referred to as the wafer burn-in). As is shown in
FIG. 6
, the probe card
201
is made from glass or the like, and includes a card body
201
a
provided with a wiring layer on a main surface (corresponding to the lower surface in FIG.
6
), and a film
201
b
having bumps made from a polyimide thin film with its edge supported by a rigid ring
202
of ceramic or the like. On the main surface of the film
201
b
having bumps, plural bumps
204
serving as probe terminals are formed in positions corresponding to respective testing electrodes of the semiconductor chips on a semiconductor wafer
203
. These bumps
204
are electrically connected with the card body
201
a
through contacts penetrating the film
201
b
having the bumps.
In the wafer burn-in using this probe card
201
, it is necessary to bring the respective bumps
204
of the probe card
201
to complete contact with the respective electrodes of the semiconductor chips formed on the semiconductor wafer
203
. For this purpose, a wafer tray
211
of a metal such as aluminum is used for holding the semiconductor wafer
203
.
In the periphery of a surface of the wafer tray
211
opposing the main surface of the probe card
201
(i.e., in the periphery of the main surface of the wafer tray
211
), a sealing ring
212
of silicon rubber or the like is provided so as to form a sealed space together with the main surface of the probe card
201
and the main surface of the wafer tray
211
. Also, the wafer tray
211
is provided, at a side portion, with a vacuum valve
213
for communicating the sealed space with the outside and for retaining a reduced pressure in the sealed space.
When the pressure within the sealed space is reduced by releasing the air through the vacuum valve
213
, the back surface of the probe card
201
and the back surface of the wafer tray
211
are pressed against each other due to the atmospheric pressure. Accordingly, the bumps
204
formed on the main surface of the film
201
b
having the bumps of the probe card
201
come closer to and are pressed against the electrodes formed on the semiconductor wafer
203
. As a result, when the probe card
201
, the semiconductor wafer
203
and the wafer tray
211
are thus integrated with one another and placed in a burn-in apparatus, the wafer burn-in can be performed.
In the burn-in apparatus
100
used for resin sealed semiconductor chips, the burn-in test of the semiconductor chips
104
is conducted at a high temperature of approximately 125° C. within the burn-in chamber
101
. Accordingly, it is necessary to put the semiconductor chips
104
placed on the BI boards
102
into the burn-in chamber
101
retained at a high temperature. On the other hand, the active devices
124
on the driver boards
123
are required to be placed at the outside of the burn-in chamber
101
in order to secure the operation of the active devices
124
. As a result, the length of the signal line
122
is elongated, and hence, the signal can be easily degraded and the apparatus is not suitable to a high speed operation test.
Furthermore, in the burn-in apparatus used in the wafer burn-in, more semiconductor chips are tested in a batch than those in the above-mentioned burn-in apparatus used for resin sealed semiconductor chips. Therefore, a load on the circuit testing apparatus is disadvantageously largely increased as compared with a conventional technique where each chip is tested.
SUMMARY OF THE INVENTION
The object of the invention is preventing the degradation of a test signal and decreasing a test load on a circuit testing apparatus.
The present inventors have found the following: In the probe card
201
of
FIG. 6
used for the wafer burn-in, a large number of semiconductor chips
104
formed on the semiconductor wafer
203
themselves generate heat during the operation. Therefore, in order to retain the semiconductor wafer
203
at a predetermined temperature, it is necessary to locally control (through a heating or endothermic operation) the temperature of merely the wafer tray
211
in contact with the semiconductor wafer
203
. Moreover, in the case where the temperature is thus controlled, the temperature of the back surface of the probe card
201
can be controlled to be lower than approximately 70° C. by appropriately controlling the ambient temperature of the probe card
201
when plural wafer trays
211
are placed in a burn-in apparatus.
In addition to the above-described findings, the present inventors have noticed that a space, which cannot be found on the conventional BI board
102
, is present on the back surface of the probe card
201
receiving the atmospheric pressure. Based on these findings and fact, the present invention has been achieved.
According to the present invention, on the back surface of a probe card (i.e., a surface other than the surface opposing the semiconductor wafer) for use in the wafer burn-in, a device for controlling or testing a semiconductor chip or a device for suppressing variation of a control signal is formed correspondingly to each chip.
Specifically, the probe card of this invention, for use in testing an electric characteristic of plural semiconductor chips formed on a semiconductor wafer in a batch at a wafer level through application of a voltage to electrodes of the plural semiconductor chips, comprises a card body; plural probe terminals disposed on a first surface of the card
Ishizaka Masaaki
Nakata Yoshiro
Oki Shinichi
Matsushita Electrical Industrial Do., Ltd.
Nguyen Vinh P.
Nixon & Peabody LLP
Studebaker Donald R.
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