Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-05-15
2004-09-14
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090
Reexamination Certificate
active
06791347
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a probe arrangement which is effective for performing a burn-in screening applied to a plurality of semiconductor devices of a wafer condition at a time. The burn-in screening is performed to enhance the reliability of semiconductor devices.
Conventionally, to enhance the reliability of semiconductor devices, the screening of semiconductor devices is performed in the following manner. Each semiconductor device is subjected to a rated or a slightly excessive voltage supplied from an electric power source. The burn-in screening takes several hours. During the burn-in screening, a pseudo signal resembling to an actual operation signal is applied to each signal input electrode, while the semiconductor device is continuously exposed to a high-temperature environment of approximately 125° C.
According to a conventional burn-in screening method, a plurality of semiconductor devices are assembled as a package and are subjected at a time to the burn-in screening.
On the other hand, a new burn-in screening method has been recently proposed. The new burn-in screening method is characterized in that the burn-in screening is applied to wafer-state semiconductor devices, such as bare chips and CSP (chip size package).
To realize the packaged burn-in screening applied to wafer-state semiconductor chips, bonding pads are used. The bonding pads serve as lead electrodes for a plurality of semiconductor chips manufactured at a time on a semiconductor wafer. A signal line is connected to the bonding pad. A signal is thus applied to the bonding pad via the signal line. Usually, the number of semiconductor chips formed together on a wafer surface is in a range from 200 to 1,000. Each semiconductor chip is provided with 20 to 40 bonding pads each being an electrode of 100 &mgr;m or a comparable micro size. Thus, the total number of signal lines connected to a single wafer raises up to a higher level of 4,000 to 40,000. Thus, accurate connection of such numerous signal lines to corresponding bonding pads is a key to succeed in the packaged burn-in screening. Regarding a technique relating to a packaged or batch contact of numerous signal lines to a semiconductor wafer, a TPS probe is disclosed in the scientific magazine “NIKKEI MICRO DEVICE”, 1997, July, from page 126.
FIG. 7
shows a conventional TPS probe card
120
which includes a platelike wiring substrate
71
, together with a ceramic ring
72
, a PCR (i.e., pressure-sensitive conductive rubber)
73
, and a bump-formed membrane
74
provided on an upper surface of wiring substrate
71
. The wiring substrate
71
is made of a glass or a comparable material having a thermal expansion coefficient similar to that of a semiconductor wafer. The wiring substrate
71
has a surface brought into contact with the PCR
73
. A signal, transmitted from the PCR
73
to the surface of wiring substrate
71
, is output to the outside via a wiring arranged on this surface of wiring substrate
71
. The PCR
73
is soft and thus has a function of absorbing the altitudinal dispersion of the bonding pads of a semiconductor chip and the bumps of TPS probe card
120
. Thus, PCR
73
ensures the transmission of signal from the bumps.
An outer diameter of ceramic ring
72
is smaller than the radial (or longitudinal) size of wiring substrate
71
. PCR
73
is located beneath the bump-formed membrane
74
and is positioned within an inner rim of ceramic ring
72
. A periphery of bump-formed membrane
74
is tightly held by the ceramic ring
72
. The bump-formed membrane
74
includes numerous bumps (
104
shown in
FIG. 10A
) formed on a membrane. Each bump provides electric connection to a corresponding bonding pad of a semiconductor wafer. PCR
73
is placed on an upper surface of wiring substrate
71
and is sandwiched from above by the bump-formed membrane
74
.
Published Japanese patent No. 2922486 discloses a practical structure for a TPS probe card consisting of the bump-formed membrane, PCR, and the wiring substrate.
More specifically, as shown in
FIGS. 10A and 10B
, a circular groove
107
is formed on the wiring substrate
71
. The ceramic ring
72
has a circular protrusion
108
formed on the lower surface thereof. The ring groove
107
engages or mates with the circular protrusion
108
when the ceramic ring
72
is assembled on the wiring substrate
71
. Thus, the circular groove
107
and the circular protrusion
108
cooperatively fix the position of ceramic ring
72
with respect to the wiring substrate
71
.
The wiring substrate
71
has external electrodes
109
formed along an end side thereof. An electric lead extends in the body of wiring substrate
71
to provide electric connection between each external electrode
109
and a corresponding inner electrode.
Numerous bumps
104
are formed on the surface of bump-formed membrane
74
. The bumps
104
are located inside the inner rim of ceramic ring
72
.
The wiring substrate
71
has screw holes
71
a
. The bump-formed membrane
74
has screw holes
74
a
. The ceramic ring
72
has screw holes
72
a
. The screw holes
71
a
,
74
a
, and
72
a
coincide with each other. The screw holes
71
a
,
74
a
, and
72
a
are the same number and have the same positional relationship.
The PCR
73
and the bump-formed membrane
74
are successively mounted on the upper surface of the wiring substrate
71
in such a manner an electrical path is formed from the bump
104
to the external electrode
109
via the PCR
73
.
The ceramic ring
72
is placed on the bump-formed membrane
74
and tightly holds or fixes the periphery of bump-formed membrane
74
.
Screws
106
are inserted into the screw holes
72
a
,
74
a
, and
71
a
across the stacked layers of ceramic ring
72
, bump-formed membrane
74
, and wiring substrate
71
. The distal end of each screw
106
is engaged in a hole
71
a
formed on the wiring substrate
71
, thereby firmly fixing the stacked layers of ceramic ring
72
, bump-formed membrane
74
, and wiring substrate
71
as TPC probe card
120
.
FIG. 8
shows the arrangement of a conventional wafer tray unit (i.e., vacuum chuck)
121
combinable with the TPS probe card
120
shown in FIG.
7
.
The wafer tray unit
121
shown in
FIG. 8
includes a wafer tray
81
, a wafer mounting base
82
, a seal ring
83
, and a vacuum valve
84
. The wafer tray
81
is a platelike member. The wafer mounting base
82
is placed on an upper surface of wafer tray
81
. The wafer mounting base
82
brings an effect of substantially raising the central portion of wafer tray
81
by an amount equal to the height of wafer mounting base
82
. A semiconductor wafer to be inspected is placed on an upper surface of wafer mounting base
82
. The seal ring
83
is made of a rubber material. The wafer tray
81
has a groove formed in an outer peripheral region thereof. The seal ring
83
is fitted into and firmly held in this groove of wafer tray
81
. When the wafer tray unit
121
is assembled with the TPS probe card
120
, the seal ring
83
provides an airtight sealing between them so as to define a vacuum chamber. The seal ring
83
holds a vacuum formed in the vacuum chamber. The vacuum valve
84
is attached to a side surface of wafer tray
81
, and is connected to a vacuum pump (not shown).
The wafer tray unit
121
shown in
FIG. 8
is assembled with the TPS probe card
120
shown in
FIG. 7
in the following manner.
FIGS. 11A and 11B
show a conventional alignment apparatus for aligning a semiconductor wafer
91
with respect to the probe card
120
.
FIG. 11A
is a plan view of the alignment apparatus, and
FIG. 11B
is a side view of the alignment apparatus.
In
FIG. 11A
, the semiconductor wafer
91
is placed on the wafer tray unit
121
. The wafer tray unit
121
has a plurality of holes opened on an upper surface thereof. The semiconductor wafer
91
is fixed on the wafer tray unit
121
by drawing a vacuum through the holes opened on the upper surface of wafer tray unit
121
. A heater
121
a
is provided in the wafer tray unit
121
together wit
Ishizaka Masaaki
Nakamura Yumio
McDermott & Will & Emery
Nguyen Vinh P.
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