Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Patent
1997-02-18
1999-06-22
Vo, Don N.
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
371 436, 371 437, H03M 1312
Patent
active
059149892
ABSTRACT:
A less complex maximum likelihood detector can be implemented in a partial response maximum likelihood (PRML) system without degrading system performance by saturating y values from a gain control loop to a smaller range before the y values are supplied to the maximum likelihood detector. A quantity "D" of a maximum likelihood detector operating in accordance with a partial response scheme has a particular relationship with respect to the maximum (ymax) of the y input values processed by the maximum likelihood detector. In some embodiments, y values from a gain control loop are saturated from a first larger range (defined by ymaxreal) to a second smaller range (defined by a value SAT) which is at least as great as the ymax of the ideal input signal (ymaxideal) for the partial response scheme. The saturated y values are provided to the maximum likelihood detector. The D of the maximum likelihood detector (given the partial response scheme and the smaller range of y values) is in a different "two to the power of an integer range" than the D would have been given the same partial response scheme but the larger range of y values.
REFERENCES:
patent: 4015238 (1977-03-01), Davis
patent: 4571734 (1986-02-01), Dolivo et al.
patent: 4609907 (1986-09-01), Adler et al.
patent: 4644564 (1987-02-01), Dolivo et al.
patent: 4829575 (1989-05-01), Lloyd
patent: 5027374 (1991-06-01), Rossman
patent: 5196849 (1993-03-01), Galbraith
patent: 5220294 (1993-06-01), Ichikawa
patent: 5220466 (1993-06-01), Coker et al.
patent: 5233482 (1993-08-01), Galbraith et al.
patent: 5241309 (1993-08-01), Cideciyan et al.
patent: 5258933 (1993-11-01), Johnson et al.
patent: 5276408 (1994-01-01), Norimatsu
patent: 5291499 (1994-03-01), Behrens et al.
patent: 5341387 (1994-08-01), Nguyen
patent: 5359631 (1994-10-01), Behrens et al.
patent: 5375145 (1994-12-01), Abbott et al.
patent: 5408502 (1995-04-01), How
patent: 5408503 (1995-04-01), Kahlman
patent: 5410556 (1995-04-01), Yeh et al.
patent: 5412669 (1995-05-01), Foland, Jr.
patent: 5414738 (1995-05-01), Bienz
patent: 5418795 (1995-05-01), Itakura et al.
patent: 5422760 (1995-06-01), Abbott et al.
patent: 5430768 (1995-07-01), Minuhin et al.
patent: 5432804 (1995-07-01), Diamondstein et al.
patent: 5432820 (1995-07-01), Sugawara et al.
patent: 5436932 (1995-07-01), Sogo et al.
patent: 5438460 (1995-08-01), Coker et al.
patent: 5444721 (1995-08-01), Okanoue et al.
patent: 5446746 (1995-08-01), Park
patent: 5450445 (1995-09-01), Ushirokawa
patent: 5453997 (1995-09-01), Roney, IV
patent: 5459679 (1995-10-01), Ziperovich
patent: 5461644 (1995-10-01), Bergmans et al.
patent: 5469452 (1995-11-01), Zehavi
patent: 5502735 (1996-03-01), Cooper
patent: 5504784 (1996-04-01), Niyogi et al.
patent: 5508993 (1996-04-01), Hayashi et al.
patent: 5509020 (1996-04-01), Iwakiri et al.
patent: 5521945 (1996-05-01), Knudson
patent: 5539780 (1996-07-01), Dutkiewicz
"Timing Recovery in Digital Synchronous Data Receivers", Kurt H. Mueller, et al., IEEE Transactions on Communications, vol. COM-24, No. 5, pp. 516-531 (May 1976).
"Fast Timing Recovery for Partial-Response Signalling Systems", F. Dolivo et al., IBM Research Division, Zurich Research Laboratory, pp. 0573-0575, 0577 CH2655-9/89/0000-0573 IEEE (1989).
"Fully Integrated Analog Filters Using Bipolar-JFET Technology", Khen-Sang Tan, et al., IEEE Journal of Solid-State Circuits, vol. SC-13, No. 6, (Dec. 1978).
"The Viterbi Algorithm", G. David Forney, Jr., Proceedings of the IEEE, vol. 61, No. 3, pp. 268-278 (Mar. 1973).
"Turbo-PRML: A Compromise EPRML Detector", Roger Wood, IEEE Transactions on Magnetics, vol. 29, No. 6, pp. 4018-4020 (Nov. 1993).
"Implementation of a Digital Read/Write Channel with EEPR4 Detection", Dave Welland, et al., IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1180-1185 (Mar. 1995).
"A High Speed, Low Power PRML Read Channel Device", Jeff Sonntag, et al., IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1186-1195 (Mar. 1995).
"An Experimental 180 Mb/sec PRML Channel for Magnetic Recording", John Hong et al., IEEE Transactions on Magnetics, vol. 27, No. 6, pp. 4532-4537 (Nov. 1991).
"A 3.0 V 40 Mb/s Hard Disk Drive Read Channel IC", Geert A. De Veirman, et al., IEEE Journal of Solid-State Circuits, vol. 30, No. 7, pp. 788-799 (Jul. 1995).
"Exact Bounds for Viterbi Detector Path Metric Differences", Paul H. Seigel, et al., CH2977-7/91/0000-1093 IEEE, pp. 1093-1096, (1991).
"Analog Front-End Architectures for High-Speed PRML Magnetic Read Channels", Patrick K.D. Pai, et al., IEEE Transactions on Magnetics, vol. 31, No. 2, (Mar. 1995).
"Implementation of PRML in a Rigid Disk/Drive", J.D. Coker, et al., IEEE Transactions on Magnetics, vol. 27, No. 6, pp. 4538-4543, (Nov. 1993).
"A Class of Partial Response Systems for Increasing Storage Density in Magnetic Recording", H.K. Thapar et al., IEEE Transactions on Magnetics, vol. Mag. 23, No. 5, pp. 3666-3668 (Sep. 1987).
"Integrating a Partial Response Maximum Likelihood Data Channel into the IBM 0681 Disk Drive", J.C. Coker, et al., Presented at the Twenty-Fourth Asilomar Conference on Signals, Systems & Computers, The Computer Society of the IEEE, vol. 2 of 2, pp. 674-677, (Nov. 1990).
"A PRML System for Digital Magnetic Recording", Roy D. Cideciyan, et al., IEEE Journal on Selected Areas in Communications, vol. 10, No. 1, pp. 38-56 (Jan. 1992).
"A Survey of Digital Phase-Locked Loops", William C. Lindsey, et al., Proceedings of the IEEE, vol. 69, No. 4, pp. 410-431 (Apr. 1981).
"Design and Performance of a VLSI 120 Mb/s Trellis-Coded Partial Response Channel", J.W. Rae, et al., IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1208-1214, (Mar. 1995).
"Error Rate Performance of Experimental Gigabit Per Square Inch Recording Components", Thomas D. Howell, et al., IEEE Transactions on Magnetics, vol. 26, No. 5, pp. 2298-2302 (Sep. 1990).
"Parallelism in Analog and Digital PRML Magnetic Disk Read Channel Equalizers", Gregory T. Uehara, et al., IEEE Transactions on Magnetics, vol. 31, No. 2, pp. 1174-1179 (Mar. 1995).
"PERD: Partial Error Response Detection", Takushi Nishiya, et al., IEEE Transactions on Magnetics, vol. 31, No. 6, pp. 3042-3044 (Nov. 1995).
"Realization of a 1-V Active Filter Using a Linearization Technique Employing Plurality of Emitter-Coupled Pairs", Hiroshi Tanimoto, et al., IEEE Solid-State Circuits, vol. SC-26, No. 7 pp. 937-945 (Jul. 1991).
"HD153061TF 130-Mbps PRNL Data Channel Processor", Hitachi Advance Information, Rev. D, pp. 1-3, 29-34, (Jul. 1995).
"A Digital Chip with Adaptive Equalizer for PRML Detection in Hard-Disk Drives", William L. Abbott, et al., ISSC94, Session 17, Disk-Drive Electronics, Paper FA 17.5 pp. 284-285 (1994).
"A 16MB/s PRML Read/Write Data Channel", Raymond A, Richetta, et al., ISSCC95, Session 5, Disk and Arithmetic Signal Processor, Paper WP 5.1, pp. 78-79 and 58-59 (1995).
"Reduced Complexity Viterbi Detector Architectures for Partial Response Signalling", Gerhard Fettweis, et al., Paper presented at Globecom Conference '95, pp. 559-563 (1995).
"Improving Performance of PRML/EPRML Through Noise Prediction", E. Eleftheriou and W. Hirt, IBM Research Division, (1996).
"Reduced Complexity Viterbi Detector Architectures for Partial Response Signalling", Gerhard Fettweis, et al., IBM Research Division, pp. 1-2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 (1995).
Shih Shih-Ming
Thapar Hemant K.
Yeung Kwok W.
NEC Electronics Inc.
Vo Don N.
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