PRML decoder for processing different channel codes with reduced

Details PRML decoder for processing different channel codes with reduced PRML decoder for processing different channel codes with reduced

1998-07-24

2000-08-29

Hindi, Nabil

Dynamic information storage or retrieval

Binary pulse train information signal

Binary signal gain processing

G11B 700

Patent

active

061118354

ABSTRACT:
In a PRML decoder, a branch metric calculator receives an input bit sequence having a multi-level multi-state characteristic precoded in a particular channel code and produces a set of branch metrics corresponding in number to amplitude levels which the input bit sequence assumes. ACS circuitry is formed of add/compare/select (ACS) circuits, adders and unit delay elements connected respectively to the ACS circuits and the adders. The ACS circuitry is arranged to respond to a channel code indication signal representing a type of the particular channel code such that, when the particular channel code is of a first tape, the ACS circuits and the associated unit delay elements combine to produce a first path select signal and most recent path metrics from the branch metrics and previous path metrics, and when the particular channel code is of a second type, the ACS circuits, the adders and the associated unit delay elements combine to produce a second path select signal and most recent path metrics from the branch metrics and previous path metrics. A path memory is responsive to the first and second path select signals and the channel code indication signal for producing an output bit sequence.

REFERENCES:
patent: 5604724 (1997-02-01), Shiokawa

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