Information security – Prevention of unauthorized use of data including prevention... – Access control
Reexamination Certificate
2004-10-06
2010-06-01
Orgad, Edan (Department: 2439)
Information security
Prevention of unauthorized use of data including prevention...
Access control
C726S026000
Reexamination Certificate
active
07730544
ABSTRACT:
A processor architecture provides for at least two simultaneous execution contexts, hardware resources having at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, and a given privileged context from among the simultaneous execution contexts that, in a privileged mode of an operating system, commands the other processor contexts by reading from and writing to registers of other contexts.
REFERENCES:
patent: 4569018 (1986-02-01), Hummel et al.
patent: 5148544 (1992-09-01), Cutler et al.
patent: 5179702 (1993-01-01), Spix et al.
patent: 5247629 (1993-09-01), Casamatta et al.
patent: 5515538 (1996-05-01), Kleiman
patent: 5892944 (1999-04-01), Fukumoto et al.
patent: 6418460 (2002-07-01), Bitar et al.
patent: 7024672 (2006-04-01), Callender et al.
patent: 7254528 (2007-08-01), Bowers et al.
patent: 7299383 (2007-11-01), David et al.
patent: 7350204 (2008-03-01), Lambert et al.
patent: 7577954 (2009-08-01), Shiota
patent: 2002/0083297 (2002-06-01), Modelski et al.
patent: 2003/0088610 (2003-05-01), Kohn et al.
patent: WO 00/43878 (2000-07-01), None
Andrew A Chien and Jay H Byun; Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor; Apr. 1, 1999; Symposium on {FPGA}s for Custom Computing Machines; IEEE.
Halfhill, T., “Arm Dons Armor: TrustZone Security Extensions Strengthen ARMv6 Architecture,”Microprocessor Report, Aug. 25, 2003, retrieved from http://www.arm.com/miscPDFs/4136.pdf>, pp. 1-4, download date Apr. 24, 2004.
Madon, D., et al., “Etude d'Implementation d'un Processeur du Type SMT (Simultaneous Multithreaded),”5thSymposium sur les Architectures Nouvelles de Machines, Rennes, Jun. 8-11, 1999, retrieved from http://lslwww.epfl.ch/pages/staff/madon/usr—pages/staff/madon/documents/sympa.pdf>, pp. 1-14, download date Apr. 13, 2004.
Marr, D., et al., “Hyper-Threading Technology Architecture and Microarchitecture,”Intel Technology Journal 6(1):1-12, Feb. 14, 2002, retrieved from http://www.intel.com/technology/itj/2002/volumne06issue01/art01—hpyer/vol6issl—art01.pdf>, download date Apr. 13, 2004.
York, R., “A New Foundation for CPU Systems Security: Security Extensions to the ARM Architecture,” May 2003, retrieved from http://www.arm.com/pdfs/TrustZone.pdf> pp. 1-8, download date Apr. 24, 2004.
Jorgenson Lisa K.
Orgad Edan
Seed IP Law Group PLLC
STMicroelectronics SA
Tarleton E. Russell
LandOfFree
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