Priority system with low speed request bus

Multiplex communications – Wide area network – Packet switching

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370 95, 364200, H04J 316

Patent

active

043131964

ABSTRACT:
A new polling apparatus for units on a shared bus of a data processing system operates with a relatively slow multi signal line request bus and a relatively slow local counter. The local counter divides each time slot into a few sub-slots. Each sub-slot is assigned to two or more units in a priority sequence and during a sub-slot the assigned units contend for access to the bus by raising signals on particular lines of the request bus according to their priority within the sub-slot.

REFERENCES:
patent: 3755628 (1973-08-01), Games et al.
patent: 3870825 (1975-03-01), Roberts et al.
patent: 3983540 (1976-09-01), Keller et al.
patent: 4120029 (1978-10-01), Steiner
patent: 4220822 (1980-09-01), Kawai et al.
IBM Tech. Disc. Bulletin, vol. 22, No. 2, Jul. 1979, pp. 863-865, "Bus Architecture . . . ".
IBM Tech. Disc. Bulletin, vol. 23, No. 4, Sep. 1980, pp. 1323-1325.

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