Priority resolution in bus orientated computer systems

Details Priority resolution in bus orientated computer systems Priority resolution in bus orientated computer systems

1984-06-12

1988-01-26

Shaw, Gareth D.

Boots, shoes, and leggings

364200, G06F 1336

Patent

active

047220724

ABSTRACT:
A priority resolution device for bus orientated computer systems. The system includes a plurality of subsystems, each connected to an associated logic circuit, as well as structure for periodically assigning to each of the subsystems together with input to the logic circuit associated therewith a priority indicating an n-bit digital signal. Sets of n signal lines are provided, one set connected to each logic circuit to carry a corresponding bit of the n-bit signal, ranging from the most significant bit (MSB) to the least significant bit (LSB). An open collector bus has n bus lines, each connected to a corresponding one of the signal lines. Each logic circuit includes comparator means for cyclically comparing the bit value on the signal lines connected to the circuit with the corresponding current bus value to produce an output signal to enable or disenable the next least significant bit comparison by the circuit, whereby the logic circuit having the last enabled line at the end of each cycle of operation enables a requested connection of its associated subsystem.

REFERENCES:
patent: 3914747 (1975-10-01), Barnes et al.
patent: 4375639 (1983-03-01), Johnson, Jr.
patent: 4418386 (1983-11-01), Vrielink
patent: 4644464 (1987-02-01), Logsdon et al.
Gibson et al., "Microcomputers for Engineers and Scientists", 1980 p. 47.

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