Priority encoder for a content addressable memory

Details Priority encoder for a content addressable memory Priority encoder for a content addressable memory

1990-06-25

1992-06-16

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG2, 36493701, 3649278, 341102, G06F 1314

Patent

active

051231050

ABSTRACT:
A priority encoder for receiving input request signals at a number of input request terminals and for providing an N-bit output binary code word indicating the binary identification number of the highest-priority, currently-active input request terminal. Each output bit of the output binary code word is provided from a respective logic circuit. Whenever any one of a first group of input request terminals, which are identified as having a logical TRUE value in a particular bit position of the N-bit output binary code word, is active, all of a second group of input request terminals, having a logical FALSE value for the particular bit position, are disabled. Sequential operation of the logic circuits for each output bit is obtained by successively delaying enablement of a logic circuit until high-order logic circuits have completed operation.

REFERENCES:
patent: 4334288 (1982-06-01), Booher
patent: 4348741 (1982-09-01), McAlister et al.
patent: 4627018 (1986-12-01), Trost et al.
patent: 4887084 (1989-12-01), Yamaguchi
patent: 4928260 (1990-05-01), Chuang et al.

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