Priority encoder and method of operation

Details Priority encoder and method of operation Priority encoder and method of operation

1992-11-27

1994-06-14

Malzahn, David H.

Boots, shoes, and leggings

G06F 700

Patent

active

053216407

ABSTRACT:
A priority encoder (12) has a most significant bit circuitry (18), a first less significant bit circuitry (20) and a second less significant bit circuitry (22). The priority encoder detects a leading one within a plurality of data bits. Each data bit is associated with a different one of a plurality of input signals. The most significant bit circuitry is coupled to a first one of the input signals and generates a first output signal and a parallel blocking signal. Both of the first output signal and the parallel blocking signal are representative in a first logic state of a leading one associated with the first signal. The first less significant bit cell is coupled to a second one of the input signals and to the parallel blocking signal. The first less significant bit cell generates a second output signal and a less significant carry signal. Both the second output signal and the less significant carry signal are representative in a first logic state of a leading one associated with the second input signal. The second less significant bit cell is coupled to a third one of the input signals, to the parallel blocking signal and to the less significant carry signal. The second less significant bit cell generates a third output signal representative in a first logic state of a leading one associated with the third input signal.

REFERENCES:
patent: 4064421 (1977-12-01), Gajski et al.
patent: 4553220 (1985-11-01), Swanson
patent: 4849920 (1989-07-01), Simpson et al.
patent: 4954978 (1990-09-01), Terane et al.
patent: 5111415 (1992-05-01), Skackleford

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