Priority encoder

Details Priority encoder Priority encoder

1998-10-21

2002-05-07

Ngo, Chuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06385631

ABSTRACT:

FIELD
The present invention relates to circuits, and more particularly, to priority encoder circuits.
BACKGROUND
Priority encoders provide output voltages indicative of the position of the leading one or zero in a binary tuple, and are used in many different types of circuits for many different applications. For high speed, low power circuits, there is a need to provide for priority encoders with low power-delay products.
An example of a priority encoder at the logic gate level using AND gates is illustrated in FIG.
1
. The priority encoder of
FIG. 1
provides the position of the leading one in a six-bit binary tuple B=(B[
0
], B[
1
], B[
2
], B[
3
], B[
4
], B[
5
]), where B[i]=1 denotes a HIGH voltage and B[i]=0 denotes a LOW voltage. The output voltages are labeled E
i
,i=0, 1, . . . 5, where only at most one E
i
is HIGH to indicate the position of the leading one in the six-bit binary tuple B.
For high speed circuits, logic gates with large fan-in are generally to be avoided, for otherwise the signal propagation delay in the circuit may be too large. In the particular example of
FIG. 1
, the fan-in is limited to four. For a six-bit priority encoder, this fan-in limitation is not necessarily a problem, for only two levels of AND gates are utilized in FIG.
1
. However, extending the circuit structure of
FIG. 1
to an n-bit priority encoder, and maintaining the fan-in limitation to four, would require └n/4┘+1 levels of AND gates, where └x┘ for some x denotes the largest integer less than or equal to x. For example, for a 32-bit priority encoder, there would be nine levels of AND gates in a circuit structure similar to that of FIG.
1
. Too many logic gate levels may lead to unacceptable signal propagation delays in high speed circuits.
Another problem for high speed circuits may be power dissipation. Dynamic power dissipation for a gate may be approximated as p
t
C
L
V
s
V
DD
ƒ
clk
, where the variables are respectively, in left-to-right order, switching probability, load capacitance, voltage swing of a signal, supply voltage, and clock frequency. For the circuit of
FIG. 1
, the voltage swing is also the supply voltage, so that V
s
=V
DD
. For the case of V
s
=V
DD
, and for a given clock frequency, load capacitance, and switching probability, the dynamic power dissipation may be reduced by reducing the supply voltage. However, signal propagation delay is approximately inversely proportional to supply voltage, so that reducing the supply voltage may lead to unacceptable signal propagation delay.
In low voltage swing circuits, the voltage swing V
s
is less than the supply voltage V
DD
. Low voltage swing circuits may be one promising way to reduce power dissipation in high speed circuits. Consequently, it is useful to provide a priority encoder with a circuit structure for which low voltage swings may be utilized and for which signal propagation paths are not unacceptably large.


REFERENCES:
patent: 4541067 (1985-09-01), Whitaker
patent: 5602545 (1997-02-01), Ishii et al.
patent: 5808483 (1998-09-01), Sako
Takayasu Sakurai et al, “Low-Power CMOS Design through VTH Control and Low-Swing Circuits,” International Symposium on Low Power Electronics and Design, Association for International Synoposium on Low Power Electronics and Design, Association for Computing Machinery and Special Interest Group on Design Automation, Monterey California, pp. 1-6 (1997).

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