Priority encoder

Coded data generation or conversion – Digital code to digital code converters – Tree structure

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Details

341160, G06F 1500

Patent

active

055112226

ABSTRACT:
A priority encoder-includes an encoder for coding an input consisting of a plurality of bits, selectors, respectively provided for bit input terminals of the encoder, for respectively receiving corresponding ones of a plurality of bits of an operand input, each of the selectors including a switch circuit to be controlled by an operand input bit, a carry line connected in series with the switch circuit and connected in series with all of the selectors, a first precharge circuit, connected to a carry line portion on one end side of the switch circuit, for precharging the carry line at a predetermined timing, a first detector which is controlled by an enable signal for designating upper bit priority and detects whether a potential of a carry line portion on an upper bit side of the switch circuit is at a discharge level, a second detector which is controlled by an enable signal for designating lower bit priority and detects whether a carry line portion on a lower bit side of the switch circuit is at a discharge level, and a third detector for detecting whether one of outputs from the first and second detectors and the operand input bit are both in an active state.

REFERENCES:
patent: 4348741 (1982-09-01), McAlister et al.
patent: 4887084 (1989-12-01), Yamaguchi
patent: 4924421 (1990-05-01), Seguchi
Noriyoshi Kuroyangi, "High Speed Arithmetic System for Multiplication and Floating Point System Calculation", Review Of The Electrical Communication Laboratory, vol. 10, No. 3-4, Mar.-Apr. 1962, pp. 207-229.

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