Priority determining circuit for non-volatile memory

Details Priority determining circuit for non-volatile memory Priority determining circuit for non-volatile memory

2000-02-08

2002-04-16

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S185110

Reexamination Certificate

active

06373781

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a priority determining circuit for a non-volatile memory formed by at least two memory banks.
More particularly, the invention relates to a priority determining circuit for non-volatile memory which controls the functional development of the memory banks that constitute the memory, ensuring their correct operation and determining, in each individual instance, interdependent priorities and synchronizations.
It is known that a non-volatile memory generally comprises a single array which is addressed from outside and is univocally associated with a read mode which allows to extract from it the information item at the chosen memory location.
Such a memory requires no particular sub-block management, since it only has to perform controls and optimizations of internal propagations of the signals.
Clearly, this architecture is preferred when no particular speed performance is required: its simplicity and compact size are the foundations of its stability.
However, when a memory is required to have extreme speed, the above solution is not satisfactory; accordingly, more complex and innovative design approaches have been devised, such as page-mode reading, parallel reading, and the so-called interleaved architecture.
In the field of extremely fast memory architectures, memories of the interleaved type are particularly important. These memories, which assume long sequences of sequential read operations, are organized so as to start two read processes which are parallel as regards the propagation complementarity characteristics and the activity of the memory.
In this manner, the two fundamental steps of a read cycle (pre-charge and evaluation) occur together between the two read processes, with a temporally “interleaved” mode.
In order to provide a memory with the above-described characteristics it is necessary to organize the array, the corresponding structures indirectly and the read circuits into two identical and distinct but independent banks. Accordingly, it is evident that there is a need to provide control and synchronization between the two perfectly identical banks in the memory which must be implemented and provided even in the absence of external pointers.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a priority determining circuit for a non-volatile memory which allows to manage the evolution of two parallel read streams in a memory, controlling its functional evolution.
Within the scope of this aim, an object of the present invention is to provide a priority determining circuit for non-volatile memories which allows to manage the evolution of the two read streams, determining which of the two banks of the memory must be set to evaluation mode and which one must be set to pre-charge mode and which one must be updated in its affected location and which one must not be updated.
Another object of the present invention is to provide a priority determining circuit for non-volatile memories which allows to suspend the interleaved mode of the memory, allowing reading with exclusively external addressings.
Another object of the present invention is to provide a priority determining circuit for non-volatile memories which allows to preset separate time intervals for updating activities between the read paths of each memory bank and the counters.
Another object of the present invention is to provide a priority determining circuit for a non-volatile memory which is highly stable, relatively easy to provide and at competitive costs.
This aim, these objects and others which will become apparent hereinafter are achieved by a priority determining circuit for a non-volatile memory formed by at least one pair of memory banks, each bank having a counter, characterized in that it comprises:
means for latching a read address of said memory;
master latch means for said address;
slave latch means for said address;
pointer means for read paths of the memory bank to be read of said memory, stimulated by said master latch means;
means for enabling a path for connecting said master latch means and said slave latch means;
means for enabling a path for connecting said slave latch means and said master latch means;
means for managing the increment of said counters which are connected to said slave latch means;
said read address of said memory being loaded by said master latch means into said slave latch means and then by said slave latch means into said master latch means alternately, said master latch means synchronizing timer means of said memory which are meant to activate sense amplifiers of said memory and said slave latch means driving said means for managing the increment of said counters, for an advancement of the read cycle of said memory.


REFERENCES:
patent: 5586081 (1996-12-01), Mills
patent: 5808944 (1998-09-01), Yoshitake

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