Priority control apparatus for a bus in a bus control system hav

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G06F 946

Patent

active

045831602

ABSTRACT:
A bus control system in which priority for the use of a bus is set in the order of an I/O device, a hardware operation unit and a data processing unit so that the use of the bus by the data processing unit is suppressed during the continuous processing operation of the hardware operation unit in order to allow high speed processing of the hardware operation unit and to allow interruption by the I/O device to permit the use of bus with higher priority without stopping the processing of the higher priority I/O device.

REFERENCES:
patent: 3200380 (1965-08-01), MacDonald et al.
patent: 3919692 (1975-11-01), Kronies et al.
patent: 4073005 (1978-12-01), Parkin
patent: 4096572 (1978-06-01), Namimoto
patent: 4214305 (1980-07-01), Tokita et al.
patent: 4237534 (1980-12-01), Felix
patent: 4318174 (1982-02-01), Suzuki et al.

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