Priority circuit for service request signals

Details Priority circuit for service request signals Priority circuit for service request signals

1980-12-08

1983-09-06

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328116, 328109, 307357, 3408255, G06F 946, H04Q 300

Patent

active

044031920

ABSTRACT:
An interlock arrangement in which each service request path comprises two inverter gates between an input and an output with a junction between the gates. Cross-coupling circuits are coupled from each junction to every other junction in each direction, each comprising an inverting gate in series with a diode. The diodes are normally reverse biased. A first to arrive request signal is forwarded to its output, and a later signal at any other input causes one diode to conduct and clamp the junction at its output, so that the signal is blocked from reaching the output until the first request signal returns to the inactive state.

REFERENCES:
patent: 3175189 (1965-03-01), Willyard et al.
patent: 4189766 (1980-02-01), Horiguchi et al.
French, "Discriminator Delays First of Four Responses", Electronics, p. 1 Nov. 13, 1975.
R. A. Henle, "N-Way Priority Circuit", IBM Tech. Discl. Bull., vol. 13, No. 10, pp. 2824-2825, Mar. 1971.

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