Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2007-09-18
2007-09-18
To, Doris H. (Department: 2616)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C711S108000
Reexamination Certificate
active
10789299
ABSTRACT:
A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each compare circuit is coupled to one of the storage elements in the array of storage elements. Each compare circuit has a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the priority signal lines. The priority logic also includes a delay circuit coupled to each of the compare circuits.
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Khanna Sandeep
Nataraj Bindiganavale S.
Pereira Jose P.
Roy Rupesh Ranen
Srinivasan Varadarajan
Blount Steven
Netlogic Microsystems Inc.
Shemwell Mahamedi LLP
To Doris H.
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