Priority circuit for a multiplexer terminal

Details Priority circuit for a multiplexer terminal Priority circuit for a multiplexer terminal

1983-09-09

1985-08-06

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 946

Patent

active

045339945

ABSTRACT:
A priority gating system is disclosed which is useful with a communication subsystem having a multiplicity of parallel input/output lines. To service these lines a priority address determination is made for all channels with 0 designating the highest priority and (n-1), the lowest in an n-channel system. Each signal line to the input/output devices will have a card select buffer serially inserted therein. All of the buffers will be enabled during the data transfer portion of the cycle. At the end of the service cycle for message transfer, the central processing unit initiates a dual pulse interrupt acknowledge command which first disables all buffers, then after a short delay, activates priority decoder circuitry. The priority decoder circuitry determines which of the n-channel input/output lines is to be serviced during the next data cycle. At the end of the dual pulse time interval, the logic card associated with the input/output line to be serviced as a result of the priority determination signifies to the central processor unit the memory location where pertinent data for that line is to be found.

REFERENCES:
patent: 3836889 (1974-09-01), Kotok et al.
patent: 4034349 (1977-07-01), Monaco et al.
patent: 4484271 (1984-11-01), Miu et al.

Affiliated with

Also associated with

Rating

Priority circuit for a multiplexer terminal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Priority circuit for a multiplexer terminal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Priority circuit for a multiplexer terminal will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-516211