Priority arbitration logic for a multi-master bus system

Details Priority arbitration logic for a multi-master bus system Priority arbitration logic for a multi-master bus system

1984-05-24

1987-01-27

Shaw, Gareth D.

Boots, shoes, and leggings

364900, G06F 1516, H04Q 900

Patent

active

046398597

ABSTRACT:
In a system having N devices all using a common data bus (CDB), a priority resolution circuit (PRC) for determining that particular device of the N devices which shall obtain control of the CDB when a device other than the particular device is attempting to obtain control of the CDB and comprising first logic common to all of the devices. A first control bus is common to every device and has a high signal level (SL) thereon when none of the devices is attempting to obtain control of the common data bus and a low SL thereon when any of the devices is attempting to obtain control of the CDB; and a second control bus is common to every device and has a low SL thereon when none of the devices has control of the CDB and a high SL thereon when any of the devices has control of the CDB. Each of the devices, including the particular device, comprises second logic for testing the SL on the first common control bus and responsive to the high SL on the first common control bus to then test the SL on the second common control bus. The second logic of the particular device is further responsive to the low SL of second common control bus to obtain control of the CDB.

REFERENCES:
patent: 4038644 (1977-07-01), Duke et al.
patent: 4366480 (1982-12-01), Van Hatten
patent: 4373183 (1983-02-01), Means et al.
patent: 4374413 (1983-02-01), Comfort et al.
patent: 4375639 (1983-03-01), Johnson, Jr.
patent: 4385382 (1983-05-01), Goss et al.
patent: 4494192 (1985-01-01), Lew et al.
patent: 4499538 (1985-02-01), Finger et al.

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