Incremental printing of symbolic information – Ink jet – Controller
Reexamination Certificate
2002-06-14
2004-11-30
Pham, Hai (Department: 2853)
Incremental printing of symbolic information
Ink jet
Controller
C347S057000, C347S005000
Reexamination Certificate
active
06824237
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a printhead, head cartridge having said printhead, printing apparatus using said printhead and printhead element substrate, and more particularly, to a printhead having a plurality of painting elements and a drive circuit for driving the printing elements aligned in a predetermined direction on an element board, a head cartridge having such a printhead, a printing apparatus using such a printhead, and a printhead substrate.
BACKGROUND OF THE INVENTION
In a printing apparatus used as an information output device for a word processor, personal computer or facsimile network and the like to print desired text or image information on paper, film or some other sheet-like printing medium, a serial printing method is in general and widespread use due to its inexpensiveness and ability to be made compact.
In order to facilitate an understanding of the present invention, a description will now be given of the composition of the printhead used in such a printing apparatus, using the example of a printhead that follows the ink jet method that uses thermal energy to print. For the printing element, this type of ink jet printhead provides heating elements, or heaters, at that portion of the head that is continuous with the nozzles that actually discharge the drops of ink. An electric current is then applied to the heaters, causing the heaters to boil the ink and forcing ink drops through the nozzles by the expansion of the bubbles formed in the ink when boiled. This type of printhead easily accommodates compact, high-density arrangements of nozzles and heaters, by means of which high-definition printing images can be obtained.
The heater board of the printhead of a printer that uses heaters for the heating element is supplied with power from the printer main unit by two power supply systems: a 10-30V, high-voltage power supply for driving the heaters, and a 5V power supply for the logic circuits that control the driving of the heaters.
The heater power source VH, together with the signal supplied to the logic circuit, is connected to the heater board from the printer via flexible substrate wiring that connects the main unit and the carriage, a contact pad (connection terminal) on the carriage that connects to the head, and tab wiring inside the printhead. The wiring and contact pad have resistance, inductance and capacitance impedance components, so fluctuations in current as the heater turns ON and OFF causes large, precipitous fluctuations in the heater power source VH voltage. This voltage fluctuation is superimposed on the logic signal via the flexible substrate wiring.
In order to prevent faulty operation of the heater board logic circuit due to the effects of noise mixed in with the logic signal, the input part of the logic circuit is provided with a Schmitt trigger that gives the threshold voltage for discriminating between high-level and low-level logic signals a hysteresis property as between the rising waveform and the falling waveform of the input signal.
FIG. 1
is a block diagram showing the circuit structure of a heater board of a typical ink jet printhead. From the printer main unit, a heater drive signal HE, latch signal LT, clock signal CLK and data signal DATA, respectively, are input from respective contact pads
510
. The data signal DATA is synchronized with the clock signal CLK and input into a shift register, and is held in a latch
505
with the input of the latch signal LT. The logical product of the output from the latch
505
and the heater drive signal (HE) is ANDED by an AND circuit
504
, and depending on that output the drive element
502
is turned ON via a buffer
503
and a heater
501
is activated (that is, driven).
In an ink jet printhead heater board circuit, a Schmitt trigger
508
is provided between each of the signal contact pads
510
and buffers
507
. The Schmitt trigger used in this type of circuit may be that which is described in Japanese Laid-Open Patent Application No. 08-039809.
A description will now be given of the operation of a Schmitt trigger with reference to
FIGS. 2A and 2B
, in a case in which the supply voltage Vdd is 5 V and the signal waveform rising and falling threshold voltages are 3.5 V and 1.5 V, respectively.
FIGS. 2A and 2B
are diagrams illustrating a Schmitt trigger and the operating characteristics thereof.
In
FIG. 2A
, reference numeral
100
denotes a MOS inverter with a threshold of 3.5 V (that is, 70% of the supply voltage Vdd), reference numeral
101
denotes a MOS inverter with a threshold of 1.5 V (that is, 30% of the supply voltage Vdd) and reference numeral
102
denotes a MOS inverter with a threshold of 2.5 V (that is, 50% of the supply voltage Vdd). Reference numerals
103
and
104
are NAND circuits, respectively.
The input-output characteristics of this circuit are as shown in
FIG. 2B
, in which, when a signal indicated by dotted line
10
is input, a flip-flop composed of NAND circuits
103
and
104
is initially reset and the output signal
111
is LOW. Then, when the input signal
110
exceeds 0.7 Vdd, the inverter
100
output becomes LOW, the NAND circuit
103
output becomes HIGH and the output signal
111
is HIGH. Next, when the input signal
110
voltage drops and the electric potential falls below 0.3 Vdd, the inverter
101
output inverts and switches to HIGH and the NAND circuit
104
output inverts to LOW, making the output signal
111
LOW.
Next, a description will be given of the composition of a signal that changes the threshold values of the MOS inverters
100
and
101
, with reference to FIG.
3
.
FIG. 3
shows the layout of a MOS inverter. As shown in the diagram, L and W show the length and width, respectively, of the MOS-construction FET gate. Additionally, reference numeral
120
denotes an input signal line input from the pad and reference numeral
121
denotes the output signal line.
In a typical MOS inverter, the ON resistance of the PMOS and NMOS is practically identical, and is designed so that the threshold is a central 0.5 Vdd. By changing the length L and width W of the gate shown in
FIG. 3
, the channel resistance value can be increased or decreased. Accordingly, with respect to the inverter
100
of
FIG. 2A
, the length and width of the gate are set so that the ON resistance (NMOS) is greater than the ON resistance (PMOS), and with respect to the inverter
101
, the length and width of the gate are set so that the ON resistance (NMOS) is less than the ON resistance (PMOS). As a result, as shown by the hysteresis characteristic of
FIG. 2B
, inverter circuits of different threshold values can be formed on the same heater board by any common logic circuit production process.
Next, a description will be given of the Schmitt trigger having hysteresis characteristics and formed by using two inverters of different thresholds as described above, with reference once again to FIG.
2
A.
Reference numeral
106
in
FIG. 2A
denotes an input pad and P
1
-P
6
denote points for indicating a voltage or a logic level. When the electric potential of the signal input from the input pad
106
changes from 0 V to 1.5 V, because the inverter
101
input signal threshold is 1.5 V the electric potential at point P
3
changes from HIGH to LOW and the electric potential at point P
4
also changes from LOW to HIGH.
Further, when the electric potential of the signal input from the input pad
106
changes from 1.5 V to 3.5 V, because the inverter
100
input threshold is 3.5 V the inverter
100
output inverts and the electric potential at point P
2
becomes LOW. As a result, the NAND circuit output (PS) electric potential level inverts to HIGH. Thus it is clear that the output P
5
becomes HIGH only after the input signal electric potential is 3.5 V. In this state, the output signal level is maintained even if the electric potential at the input pad rises further.
If the electric potential of the signal input from the input pad
106
falls from 5 V to 0 V, then the inverter
100
with an input threshold of 3.5 V inverts before the inve
Furukawa Tatsuo
Hirayama Nobuyuki
Imanaka Yoshiyuki
Nguyen Lam
Pham Hai
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