1992-07-02
1995-11-28
Powell, Mark R.
G06F 314
Patent
active
054715628
ABSTRACT:
A source data latch circuit for latching data which are read-in from a DRAM is provided. A data latch circuit for latching one-byte data generated by a CPU and an overflowing bit storing circuit for storing overflowing data through a three-bit shift are provided. At a composing circuit, data latched by the latch circuit at a previous time and stored in the overflowing bit storing circuit and the present data latched by the latch circuit are composed. At an OR circuit, the composed data and data with respect to which an OR is obtained are written into RAM.
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Morikawa Yusuke
Ohmi Ikuhiro
Shibata Kouichi
Garcia Gabriel
Mita Industrial Co. Ltd.
Powell Mark R.
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