Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-05-01
2002-07-23
Paladini, Albert W. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000, C361S750000, C361S762000
Reexamination Certificate
active
06423905
ABSTRACT:
TECHNICAL FIELD
The present invention relates, in general, to the construction of printed wiring boards and, in particular, to protecting against failures in the plated through holes in printed wiring boards that are caused by changes in temperature.
BACKGROUND OF THE INVENTION
Plated through holes are often formed in printed wiring boards. Such plated through holes are subject to failure over time due to fatigue caused by the cyclic strains that are the result of changing temperatures during fabrication, operation, or storage. These strains arise because of a mismatch in the coefficients of thermal expansion (CTE) between two materials: the metal forming the barrel of the plated through hole, which is usually copper having a CTE of approximately 17 ppm/° C., and the out-of-plane CTE of the dielectric material used in the printed wiring board, which is typically greater than 40 ppm/° C.
Multi-layer printed wiring boards typically are constructed by laminating several layers of dielectric material, with metal interconnection circuitry on one or usually both sides, using uncircuitized layers of a similar dielectric material to bond the ciruitized layers together. In microvia build-up arrangements, additional layers can be added sequentially by laminations, curtain, roller or screen coating or other methods known to those skilled in the art. The various layers of circuitry then are electrically interconnected by first drilling holes that intersect the circuit features that are to be connected and then plating the walls of the holes with metal (creating plated through holes) to form the connections. The hollow cylindrical hole wall metal that is formed is known to those skilled in the art as a “barrel.” This plating also connects the hole wall metallization (i.e. the barrel) with metal on the front and back exterior surfaces of the laminated structure. The exterior surface metal is usually patterned to provide lands surrounding the plated through holes which are larger than the diameters of the holes.
FIG. 1
is a schematic cross-section view of a typical, conventional printed wiring board substrate
10
. Printed wiring board substrate
10
has a glass reinforced epoxy laminate
12
and inner copper planes
14
and
16
. Inner copper plane
14
is connected to a plating
18
of a through hole
20
, while inner copper plane
16
has a clearance opening and is not connected to plating
18
of through hole
20
.
Plating
18
is composed of a first land
18
a,
a second land
18
b,
and a barrel
18
c.
As the printed wiring board of
FIG. 1
is exposed to temperature changes, possibly as great as −25° C. to +115° C., strains arise in plating
18
that can result in failures. With thinner printed wiring boards, the failure is likely to occur where first land
18
a
or second land
18
b
meet barrel
18
c
and, with thicker printed wiring boards, the failure is more likely to occur at or near the middle of barrel
18
c.
The dielectric materials used to construct multi-layer printed wiring boards are usually thermosetting organic polymers, most often epoxies. These polymers have coefficients of thermal expansion in the range of about 50 ppm/° C. to 80 ppm/° C. below the glass transition temperature (T
g
) and as high as 200 ppm/° C. to 400 ppm/° C. above T
g
. To minimize or eliminate entirely the thermally induced strains in the copper due to this CTE mismatch, the organic dielectrics are reinforced with low expansion fibers. The most common reinforcement is woven fiber glass cloth, but non-woven fiber glass fibers, woven aramid fibers, and non-woven aramid fibers also are used. The ratio of organic polymer to reinforcement fiber is normally chosen to give a composite CTE, in the plane of the dielectric layer, of about 20 ppm/° C. or lower. This choice reduces the strains in, and the potential fatigue cracking of, the copper circuit lines.
The reinforcement also improves the mechanical robustness of the dielectric layers, as well as the finished printed wiring boards. Because of the anisotropic nature of the fiber reinforcement, the out-of-plane CTE gets little, if any, reduction due to the reinforcement. As a result, the copper barrels of the plated through holes are subjected to cyclic strains when the printed wiring boards are subjected to thermal excursions, especially excursions above T
g
such as those during soldering operations for component assembly. These cyclic strains can lead to fatigue cracking of the barrels of the plated through holes resulting in open circuits and product failure. The thermal cycle cracking problem becomes worse with thicker printed wiring boards, smaller diameter plated through holes and thinner plating in the barrels of the plated through holes. The need for increased interconnection density in printed wiring boards drives all of these factors in the direction that decreases thermal cycle fatigue life.
The plated through hole fatigue problem is generally recognized within the industry. Most of the known attempts to solve the problem, however, drive one or more of the causative factors (e.g. structure thickness, plated through hole diameter, plated through hole barrel metal thickness) in a direction opposite to that desired for higher-density printed wiring boards.
U.S. Pat. No. 4,791,248 issued to Oldenettel describes a method of placing a plated through hole in a printed circuit board having a conductive core. In this patent, an insulating collar has a CTE closer to the conductive core than the CTE of epoxy. The object is to match CTE values. Thermal shock tolerance is achieved by filling oversized through holes with glass-filled resin and plating the inner surfaces of holes drilled in the filling resin.
U.S. Pat. No. 5,900,674 issued to Wojnarowski et al. teaches an interface structure for electronic devices. A floating pad is constructed above the metallized surface of a printed circuit board. More specifically, the patent describes an interface structure for electronic devices having a surface with an electrically conductive pad, a compliant coating over the surface with a via extending to the conductive pad, a metallization pattern over the compliant coating and extending into the via, and a low-modulus dielectric interface layer overlaying the compliant coating.
U.S. Pat. No. 4,658,332 issued to Baker et al. teaches a printed circuit board having a compliant layer to reduce the thermal mismatch between the printed circuit board and a lead-less chip carrier. The compliant layer is sandwiched between a pattern of conductors and an insulating layer, providing “floating” component mounting pads to reduce the carrier stresses. The elasticity of the compliant layer provides mechanical decoupling for minimizing stresses on solder joints.
U.S. Pat. No. 5,473,119 issued to Rosenmayer et al. teaches a stress-resistant circuit board. The circuit board resists shear stress caused by the unequal CTE of a mounted electronic component and the circuit board on which the component is mounted. The circuit board is described as a support layer, a shear stress-relieving layer, and a conductive layer. The disclosed arrangement is similar to that of the '332 patent. Rosenmayer et al. expand the modulus of elasticity of the compliant material, however, from 20,000 to 50,000 psi.
Japanese Published Patent Application No. 09161409, filed on behalf of Seiji, is directed to a printed wiring board. Seiji seeks to solve the problem of cracking when the board is subjected to repeated heating and cooling tests. Seiji appears to eliminate cracking in the board by forming circuits on both sides of the board and providing a plated through hole making contact to both the upper and lower layers. The holes are inclined through the board and are filled to increase life. The resin filling the plated through hole has a CTE different from that of the board. There is no compliant or resilient layer described in the printed circuit board.
The high-density printed wiring board disclosed by Hedrick et al. in IBM Application Ser. No. 08/833,614 (Filed Apr. 8, 1997) has a
Brodsky William L.
Knadle Kevin T.
Lauffer John M.
Powell Douglas O.
Russell David J.
Fraley, Esq. Lawrence R.
Paladini Albert W.
Ratner & Prestia
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