Compositions – Electrically conductive or emissive compositions – Free metal containing
Reexamination Certificate
2001-02-26
2004-02-17
Gupta, Yogendra N. (Department: 1751)
Compositions
Electrically conductive or emissive compositions
Free metal containing
C252S500000, C252S511000, C252S520300, C523S400000, C523S443000, C523S444000, C523S458000, C523S439000
Reexamination Certificate
active
06692664
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fillings for vias or holes in printed circuit boards, and more particularly, to a conductive paste for filling vias that is capable of reducing metal oxide present on the conductive substrate of printed circuit boards.
BACKGROUND OF THE INVENTION
Printed circuit boards (PCBs), also called printed wiring boards (PWBs), are used extensively in the computer hardware field for constructing electronic circuits. Chip carriers containing electronic components are placed on top of a PCB so that pins extending from the bottom of the chip carrier contact corresponding copper pads on the top surface of the PCB. The PCB usually contains several levels of circuitry in addition to a top layer. Each level of circuitry actually consists of two separate physical layers, a laminate layer and a pre-preg layer. The laminate layers contain electrical conductors on their surface. The pre-preg layers are typically a “B-staged” or partially cured fiberglass reinforced polymer. The laminate layers are imprinted or etched with copper pads and conductors that form a circuit pattern on each level of circuitry. Copper etchings provide the connections for electrical communication within each level of circuitry, however, another means is necessary for providing inter-level communication. This is generally accomplished by plated-through holes extending through and between several levels of circuitry.
A common procedure is to stack up all the layers of the PCB and to drill holes through the entire stack-up wherever an inter-level connection is desired. Therefore, even if an inter-level connection is needed from only one layer to the next, a hole is drilled through the entire stack-up. The hole is then electro-plated with copper during processing in order to groove an electrical conduction path through the hole. Unfortunately, it is common practice for copper conductors, which carry signals to and from other sources and destinations, to be routed around plated-through holes which were created for inter-level conductance to conductors on completely different circuit layers.
The use of plated-through holes leads to several other problems and disadvantages. First, copper plating, which takes a significant amount of time, must be performed in a separate step during the processing of the PCB. Also, copper has a different expansion rate when heated than the fiberglass polymer which is used in the pre-preg layer. As a result, plated-through holes are susceptible to cracking with temperature fluctuations.
The second artificial limit on hole size is the electroplating process. Small diameter holes are much more difficult to electroplate than larger ones. The costs of electroplating increase rapidly as hole diameter decreases. A typical PCB is a 50 mm pitch. The term 50 mm pitch refers to the distance between the center of adjacent conductors or adjacent pads, which is 50 mm. On a typical 50 mm pitch board, the copper pads that provide contacts for the pins of chip carriers are very small, approximately 20 mm by 35 mm. A circuit board designer is faced with the choice of high electroplating costs as well as using a very small diameter drill bit that will need to be replaced frequently, or finding some way to provide for larger holes. Typically a copper conductor is etched onto the PCB leading from copper pads to plated-through holes which are placed elsewhere on the PCB where there is enough room to place the holes on a 100 mm pitch. This is called fanout. A designer often makes a compromise in which only half of the contacts pads are fanned out to a 100 mil pitch. The fanned out holes typically have a 35 mm diameter. The remaining holes have diameters of approximately 18 mm and are drilled through every other pad, thereby providing holes on a 100 mm pitch. With fanout, not only do the larger holes take up more routing space than is necessary but the copper etches leading from the contact pads to the holes also occupy valuable routing area. In addition, fanout adds signal length which increases propagation delay as well as noise (cross-talk) vulnerability.
Another disadvantage of using larger holes is fewer etched conductors can be routed between holes. For instance, on a typical 50 mm pitch board, one or two conductor paths can be routed between holes, and this number might be increased to three or four copper conductors if not for the artificial limitation on hole diameter. Using fanout also limits the density at which surface mounted components may be placed because fanout holes occupy additional space on the top circuitry layer of the PCB.
Some prior art methods for improving the routing density on PCBs include the use of blind and buried vias. Blind vias are holes selectively drilled only in certain PCB layers and enclosed by the PCB stack-up lamination process step. Buried vias refer to those blind vias that do not connect to either the top or bottom circuitry level, i.e., that are buried in the stack-up. This process permits the movement of a plated-through hole from an undesirable position, but interconnection to the enclosed blind via still must be made by connecting the blind via to a plated-through hole. Also, the layers with the blind vias must be predrilled and pre-plated prior to the lamination step, thereby adding further complexity and cost to the fabrication process.
The typical processing of a PCB starts with the step of printing and etching a conductor pattern on each individual PCB laminate layer. The next step is to stack up the laminate layers with pre-preg layers in between each laminate layer. The pre-preg layers basically act as a bonding surface between the laminate layers. The plated-through holes are then drilled through the stack-up in preparation for copper electroplating. After the separate electroplating step, the board is cured.
Plated-through holes commonly receive pins or contacts from integrated circuits (ICs) or chip carriers that may be soldered within the plated-through hole in order to electrically connect an element to the PCB. The process of forming plated-through holes commonly involves electroless copper plating of the printed circuit board and the holes or vias in the printed circuit board. This process is expensive and only coats the vias inside surface, leaving behind a hole or via in the printed circuit board. In applications where it is not desired to insert a contact or pin within the plated-through hole and only to use the hole to carry electrical signals from one side of the board to the other side of the board, it is desirable to completely fill the hole so that a smooth planar surface remains on both sides of the printed circuit board.
Polymer thick film (PTF) via plug materials prevent the entrapment and bleed-through of material in plated-through holes, as well as increase surface area, thermal management, and padless via technology for BGA and surface mount technology. Conductive PTF materials consist of metallic particles, an organic vehicle to bind them together and promote adhesion of the paste to the substrate, and a volatile solvent that is removed during a cure or drying step.
Choice of metal filler is a major consideration. The conductivity of copper-based polymer thick film conductors is often unstable and deteriorates with age. Silver, on the other hand, has a good reliability record in polymer thick films in regard to conductivity. Silver migration, however, needs to be avoided in applications. To reduce cost, silver plated copper powder can be used, which can reduce conductivity compared to pure silver particles.
A significant problem in the use of via fillers is formation of metal oxides. Metal-oxides can form between the via filler and the etchings on laminate boards carrying signals to PCB components. These metal-oxides, such as copper oxide, reduces electrical conductivity. These metal oxides appear as a ring around the via filler at the interface between the filler material and the copper substrate of the PCB.
A solution has been to use fluxing agents to remove metal oxides and prom
Blank Rome LLP
Gupta Yogendra N.
Hamlin Derrick
Methode Electronics Inc.
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