Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-08-07
2002-01-29
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C029S830000, C361S779000, C427S096400, C428S209000
Reexamination Certificate
active
06342682
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a printed wiring board wherein a conductor pad with larger area than the area of an opening such as a photovia land and a through hole land is provided between plural openings where no conductor exists in a conductive pattern which is formed in a mesh on a single side or double sides of a base material and each opening is filled with a filling resin layer, particularly relates to a reliable printed wiring board wherein a circuit pattern provided on the upper face of an interlayer insulating layer formed on the printed wiring board and a conductor pad can be securely connected without causing disconnection by substantially equalizing the quantity of resin with which each opening is filled throughout the printed wiring board.
The present invention also relates to a printed wiring board wherein a via hole opposite to a conductor pad or a land is provided by forming a photosensitive interlayer insulating layer on a base material on which a predetermined circuit pattern including a metallic area with large area such as a power plane and a ground plane is formed and developing the interlayer insulating layer after it is exposed via a mask film, particularly relates to a printed wiring board wherein light dispersed by a metallic area which is a power plane or a ground plane is prevented from being incident to an interlayer insulating layer which exists under the mask area of a mask film when a via hole is formed opposite to a conductor pad or a land by exposing the interlayer insulating layer via a mask film, as a result, the metallic area is securely exposed and simultaneously, a via hole can be formed and a manufacturing method thereof.
Further, the present invention relates to a multilayer printed wiring board wherein a connection pad formed on a core material and a pattern on an interlayer insulating layer provided on the core material are connected via a via hole and a connection pad formed on an interlayer insulating layer and a pattern on another interlayer insulating layer are connected via a via hole, particularly relates to a reliable multilayer printed wiring board wherein when a photosensitive interlayer insulating layer is exposed with a mask film stuck on it and developed by devising the shape of a connection pad formed on a core material or on an interlayer insulating layer so as to form a via hole, the via hole and the connection pad can be stably connected even if misregistration occurs between the connection pad and the mask film.
2. Description of Related Art
(1) Heretofore, for a multilayer printed wiring board for example, a copper-clad laminate
200
on which a copper layer
202
is clad on a single side (or double sides) of an electrical insulating core material
201
is used for a base material as shown in
FIG. 28. A
conductor circuit is formed in such a copper-clad laminate
200
by laminating a photosensitive dry film where the pattern of the conductor circuit is printed on the surface of the copper layer
202
and performing etching processing after exposure and development and
FIG. 29
shows such a copper-clad laminate
200
where the conductor circuit
203
is formed from the copper layer
202
.
When the conductor circuit
203
is formed in the copper-clad laminate
200
, an exposed area (an opening)
204
in which the core material
201
is exposed between the conductor circuits
203
is simultaneously formed as shown in
FIG. 29. A
resin layer
205
is formed in such an exposed area
204
as shown in
FIG. 30
by applying and hardening electrical insulating filling resin and after the filled resin layer
205
is hardened, the respective surfaces of the conductor circuit
203
and the filled resin layer
205
are smoothed by polishing so as to prevent the failure of exposure and development of a conductor circuit
207
shown in
FIG. 33
formed on the conductor circuit
203
.
However, as shown in
FIG. 31
, when area required by a pad
203
L to which the upper conductor circuit
207
shown in
FIG. 33
is connected cannot be secured by the conductor circuit
203
in a mesh if a pattern formed by the conductor circuits
203
formed in the copper-clad laminate
200
is in a mesh (often in the case of a power pattern and a ground pattern), the area of the opening of the exposed area
204
L around the pad
203
L is reduced so as to secure the above area required by the pad
203
L and therefore, the area of the opening of the exposed area
204
L around the pad
203
L is smaller than that of another exposed area
204
.
As a result, the quantity of resin which can fill the exposed area
204
L around the pad
203
L is smaller than that of resin which can fill another exposed area
204
and when the exposed areas
204
and
204
L are filled with resin, the quantity of filled resin overflowing from the exposed area
204
L around the pad
203
L is more than that overflowing from another exposed area
204
and even if the respective surfaces of the conductor circuit
203
and the filled resin layer
205
are polished so that they are smooth after the filled resin is hardened to be the filled resin layer
205
, the filled resin
205
L is left on the pad
203
L as shown in
FIG. 32
which is a sectional view viewed along a line B-B′ in FIG.
31
.
As shown in
FIG. 33
, an electrical insulating adhesion layer
206
is laminated on the conductor circuit
203
in a state in which the filled resin
205
L is left on the pad
203
L and when the conductor circuit
207
formed on the conductor circuit
203
is connected to the pad
203
L which is a part of the conductor circuit
203
via a via hole P formed in the adhesion layer
206
, there is a problem that the failure of conduction is caused between the conductor circuit
203
and the conductor circuit
207
because the electrical insulating filled resin
205
L exists between the pad
203
L and the conductor circuit
207
.
The mesh pattern formed by the conductor circuits
203
may be formed on an adhesive layer for electroless plating which also functions as the interlayer insulating material of a built-up type multilayer printed wiring board. In this case, in the mesh pattern the area of the opening of the exposed area
204
L around the pad
203
L is reduced. A plating resist is provided to this opening
204
L, the reduction of the area causes the reduction of contact area with the adhesive layer for electroless plating and also causes the peeling of the plating resist and the interlayer insulating material formed on it.
(2) Heretofore, for a printed wiring board provided with a via hole, a variety of printed wiring boards are proposed. Referring to
FIGS. 34 and 35
, a method of manufacturing this type of printed wiring board will be described below.
FIG. 34
is a sectional view showing a base material and
FIG. 35
is a plan showing the base material.
To manufacture a printed wiring board
220
shown in
FIG. 38
, first, a base material
221
shown in
FIGS. 34 and 35
is produced. The base material
221
is produced by performing predetermined etching after a metallic area
222
with large area such as a power plane and a ground plane, a connecting pad
223
with normal area and copper foil which is to be a predetermined circuit pattern
224
on a copper-clad laminate formed by laminating copper foil on a single side or double sides are coated with an etching resist.
Afterward, an interlayer insulating layer
225
shown in
FIG. 36
is formed by applying photosensitive resin on the base material
221
together with the metallic area
222
, the connecting pad
223
and the circuit pattern
224
. Further, after a mask film
227
is exposed in a state in which it is stuck on the interlayer insulating layer
225
with a predetermined mask area
228
shown in
FIG. 37
formed in the mask film
227
corresponding to the metallic area
222
and the connecting pad
223
, a via hole
226
is formed corresponding to the metallic area
222
and the connecting pad
223
. Afterward, a continuous circuit pattern
229
including the in
Kawamura Yoichiro
Mori Yoji
Ibiden Co. Ltd.
Oliff & Berridg,e PLC
Paladini Albert W.
LandOfFree
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