Printed-wiring board and electronic device

Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement

Reexamination Certificate

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Details

C174S262000, C174S263000, C361S760000, C361S779000

Reexamination Certificate

active

06940023

ABSTRACT:
The present invention provides a board ensuring no peel-off of a wall and a land, even if a part is soldered to the board with lead-free solder. The board10is comprised of N (N≧3) layer patterns electrically insulated from one another, and is formed with a through-hole14into which an electrode19of an electronic part18is to be inserted. An external land15is formed on a surface of each of the first and N-th layer patterns. An electrically conductive layer17is formed on an inner wall of the through-hole14such that the electrically conductive layer is electrically connected to the external land15of each of the first and N-th layer patterns. The electronic part18is fixed in the through-hole14with lead-free solder20filled in the through-hole14. At least one internal land16extending from the electrically conductive layer17is formed in the same layer as a M-th layer pattern (2≦M≦(N−1)). The internal land16is not electrically connected to the M-th layer pattern.

REFERENCES:
patent: 5743004 (1998-04-01), Chobot et al.
patent: 6521842 (2003-02-01), Brinthaupt et al.
patent: 6849805 (2005-02-01), Honda et al.
patent: 63-264341 (1988-11-01), None
patent: 03-165093 (1991-07-01), None
patent: 03-165094 (1991-07-01), None
patent: 04-354180 (1992-12-01), None
patent: 06-120667 (1994-04-01), None
patent: 06-232562 (1994-08-01), None
patent: 09-008443 (1997-01-01), None
patent: 10041605 (1998-02-01), None
patent: 2001-024297 (2001-01-01), None
patent: 2001-332851 (2001-11-01), None
Comuter translation of Japanese Publication JP10041605A.

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